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CC2510FX / CC2511Fx
True System-on-Chip with Low Power RF Transceiver and 8051 MCU
Applications
* * * * * Wireless keyboard and mouse Wireless voice-quality audio CC2511Fx: USB dongles Remote controls Wireless sports and leisure equipment * * * * * Point-of-sale systems Active RFID and asset tracking systems Home and building automation Low power telemetry 2.4 GHz ISM/SRD band systems
Product Description
The CC2510FX/CC2511Fx is a low-cost true system-on-chip (SoC) device designed for lowpower and low-voltage wireless communication applications. The CC2510FX/CC2511Fx combines the excellent performance of the state-of-the-art RF transceiver CC2500 with an industry-standard enhanced 8051 MCU, 8/16/32 kB of in-system programmable flash memory, 1/2/4 kB of RAM and many other powerful features. The CC2510FX/CC2511Fx is available in six different versions: CC2510F8 and CC2511F8 with 8 kB of Flash and 1 kB of RAM, the CC2510F16 and CC2511F16 with 16 kB of Flash and 2 kB of RAM, and CC2510F32 and CC2511F32 with 32 kB of Flash and 4 kB of RAM. The CC2510FX/CC2511Fx is highly suited for systems where very low power consumption is required. This is ensured by several advanced low-power operating modes. The CC2511Fx adds a full-speed USB interface to the feature set of the CC2510FX. Interfacing to a PC using the USB interface is quick and easy, and the high data rate (12 Mbps) of the USB interface avoids the bottlenecks of RS232 or low-speed USB interfaces.
DIGITAL ANALOG MIXED VDD (2.0 - 3.6 V) DCOUPL
RESET_N XOSC_Q2 XOSC_Q1 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0
P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0
DP DM
RF_P
RF_N
Key Features
* * * * * * * * * * * * * High performance and low power 8051 microcontroller core. High-performance CC2500 RF transceiver based on the market-leading CC2500 Frequency band: 2.4 GHz 8/16/32 kB in-system programmable flash 1/2/4 kB RAM + 1 kB USB FIFO (CC2511Fx) Full-Speed USB Controller (CC2511Fx ) I2S interface 8-14 bits ADC with up to eight inputs 128-bit AES security coprocessor Powerful DMA functionality Two USARTs 16-bit timer with configurable mode Three 8-bit timers * * * * * * * * * * * * Hardware debug support 21 (CC2510FX ), 19 (CC2511Fx ) GPIO pins Wide supply voltage range (2.0V - 3.6V) High sensitivity (-100 dBm at 10 kbps) Programmable data rate up to 500 kbps Low current consumption (RX: 22 mA, TX: 23 mA, with MCU running at 26 MHz) MCU current consumption 270A/MHz Programmable output power up to 1 dBm for all supported frequencies Digital RSSI / LQI support Excellent receiver selectivity and blocking performance 0.3 A consumption in lowest power mode RoHS compliant 6x6mm QLP36 package
This data sheet contains preliminary data, and supplementary data will be published at a later date. Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. The product is not yet fully qualified at this point.
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 1 of 252
CC2510FX / CC2511Fx
Table of Contents
1 2 3 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 8 9 9.1 9.2 10 11 11.1 11.2 11.3 11.4 11.5 12 12.1 12.2 12.3 12.4 ABBREVIATIONS.....................................................................................................................5 REFERENCES ...........................................................................................................................6 REGISTER CONVENTIONS...................................................................................................6 FEATURES (CONTINUED FROM FRONT PAGE).............................................................8 HIGH-PERFORMANCE AND LOW-POWER 8051-COMPATIBLE MICROCONTROLLER .......................8 8/16/32 KB NON-VOLATILE PROGRAM MEMORY AND 1/2/4 KB DATA MEMORY..........................8 FULL-SPEED USB CONTROLLER (CC2511FX ) ................................................................................8 I2S INTERFACE..............................................................................................................................8 HARDWARE AES ENCRYPTION/DECRYPTION................................................................................8 PERIPHERAL FEATURES .................................................................................................................8 LOW POWER..................................................................................................................................8 2.4 GHZ RADIO WITH BASEBAND MODEM .....................................................................................9 ABSOLUTE MAXIMUM RATINGS.....................................................................................10 OPERATING CONDITIONS .................................................................................................10
CC2510FX OPERATING CONDITIONS .............................................................................................10 CC2511FX OPERATING CONDITIONS ..............................................................................................10
ELECTRICAL SPECIFICATIONS.......................................................................................11 GENERAL CHARACTERISTICS ......................................................................................................12 RF RECEIVE SECTION..................................................................................................................13 RF TRANSMIT SECTION ...............................................................................................................14 26/48 MHZ CRYSTAL OSCILLATOR.............................................................................................15 32.768 KHZ CRYSTAL OSCILLATOR ............................................................................................15 LOW POWER RC OSCILLATOR.....................................................................................................16 HIGH SPEED RC OSCILLATOR .....................................................................................................16 FREQUENCY SYNTHESIZER CHARACTERISTICS............................................................................17 ANALOG TEMPERATURE SENSOR ................................................................................................17 8-14 BIT ADC..............................................................................................................................18 CONTROL AC CHARACTERISTICS................................................................................................19 SPI AC CHARACTERISTICS..........................................................................................................20 DEBUG INTERFACE AC CHARACTERISTICS .................................................................................21 PORT OUTPUTS AC CHARACTERISTICS .......................................................................................21 TIMER INPUTS AC CHARACTERISTICS.........................................................................................22 DC CHARACTERISTICS ................................................................................................................22 PIN AND I/O PORT CONFIGURATION .............................................................................23 CIRCUIT DESCRIPTION ......................................................................................................27 CPU AND PERIPHERALS ..............................................................................................................28 RADIO .........................................................................................................................................29 POWER CONTROL................................................................................................................30 APPLICATION CIRCUIT......................................................................................................31 BIAS RESISTOR ............................................................................................................................31 BALUN AND RF MATCHING .........................................................................................................31 CRYSTAL.....................................................................................................................................31 USB (CC2511FX) ..........................................................................................................................31 POWER SUPPLY DECOUPLING....................................................................................................... 31 8051 CPU...................................................................................................................................35 8051 CPU INTRODUCTION ..........................................................................................................35 RESET..........................................................................................................................................35 MEMORY .....................................................................................................................................35 SFR REGISTERS...........................................................................................................................39
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 2 of 252
CC2510FX / CC2511Fx
12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 13.12 13.13 13.14 13.15 13.16 14 14.1 14.2 15 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 15.11 15.12 15.13 15.14 15.15 15.16 15.17 15.18 15.19 16 16.1 17 18 19 20 CPU REGISTERS ..........................................................................................................................42 INSTRUCTION SET SUMMARY ......................................................................................................44 INTERRUPTS ................................................................................................................................49 OSCILLATORS AND CLOCKS .........................................................................................................60 DEBUG INTERFACE......................................................................................................................60 RAM...................................................................................................................................64 FLASH MEMORY..................................................................................................................64 MEMORY ARBITER ..............................................................................................................64 PERIPHERALS........................................................................................................................66 I/O PORTS ....................................................................................................................................66 DMA CONTROLLER ....................................................................................................................84 16-BIT TIMER, TIMER 1 ...............................................................................................................97 MAC TIMER (TIMER 2) .............................................................................................................111 SLEEP TIMER .............................................................................................................................113 8-BIT TIMER 3 AND TIMER 4 ......................................................................................................116 ADC..........................................................................................................................................127 RANDOM NUMBER GENERATOR................................................................................................133 AES COPROCESSOR ..................................................................................................................135 POWER MANAGEMENT ......................................................................................................140 POWER ON RESET .............................................................................................................144 WATCHDOG TIMER............................................................................................................145 USART .............................................................................................................................147 I2S ....................................................................................................................................158 USB CONTROLLER ............................................................................................................166 FLASH CONTROLLER .........................................................................................................184 CRYSTAL OSCILLATOR ...................................................................................................190
CC2510FX CRYSTAL OSCILLATOR..............................................................................................190 CC2511FX CRYSTAL OSCILLATOR ..............................................................................................190
RADIO.....................................................................................................................................191 COMMAND STROBES.................................................................................................................. 191 RADIO REGISTERS .....................................................................................................................193 INTERRUPTS ..............................................................................................................................193 TX/RX DATA TRANSFER ..........................................................................................................195 DATA RATE PROGRAMMING .....................................................................................................196 RECEIVER CHANNEL FILTER BANDWIDTH ................................................................................197 DEMODULATOR, SYMBOL SYNCHRONIZER AND DATA DECISION..............................................197 PACKET HANDLING HARDWARE SUPPORT ................................................................................198 MODULATION FORMATS ...........................................................................................................202 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION..................................203 FORWARD ERROR CORRECTION WITH INTERLEAVING.......................................................207 RADIO CONTROL ...............................................................................................................208 FREQUENCY PROGRAMMING .............................................................................................211 VCO..................................................................................................................................211 OUTPUT POWER PROGRAMMING .......................................................................................212 SELECTIVITY GRAPHS .......................................................................................................213 ANTENNA INTERFACE........................................................................................................216 SYSTEM CONSIDERATIONS AND GUIDELINES.....................................................................216 RADIO REGISTERS .............................................................................................................219 VOLTAGE REGULATORS .................................................................................................241 VOLTAGE REGULATOR POWER-ON............................................................................................241 RADIO TEST OUTPUT SIGNALS......................................................................................241 EVALUATION SOFTWARE ...............................................................................................243 REGISTER OVERVIEW......................................................................................................244 PACKAGE DESCRIPTION (QLP 36).................................................................................247
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 3 of 252
CC2510FX / CC2511Fx
20.1 20.2 20.3 20.4 20.5 21 22 22.1 22.2 23 24 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 36)............................................................248 PACKAGE THERMAL PROPERTIES ...............................................................................................248 SOLDERING INFORMATION ........................................................................................................248 TRAY SPECIFICATION................................................................................................................. 248 CARRIER TAPE AND REEL SPECIFICATION ..................................................................................249 ORDERING INFORMATION..............................................................................................249 GENERAL INFORMATION................................................................................................250 DOCUMENT HISTORY ................................................................................................................250 PRODUCT STATUS DEFINITIONS ................................................................................................250 ADDRESS INFORMATION.................................................................................................251 TI WORLDWIDE TECHNICAL SUPPORT......................................................................251
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 4 of 252
CC2510FX / CC2511Fx
1 Abbreviations
ADC AES AGC ARIB BCD BER CBC CBC-MAC CCA CCM CFB CFR CMOS CPU CRC CTR CW DAC DMA DSM ECB EM ENOB EP{0-5} ESD ESR ETSI FCC FFCTRL FIFO HSSD I2S I/O I/Q IEEE IF IOC
Analog to Digital Converter Advanced Encryption Standard Automatic Gain Control Association of Radio Industries and Businesses Binary Coded Decimal Bit Error Rate Cipher Block Chaining Cipher Block Chaining Message Authentication Code Clear Channel Assessment Counter mode + CBC-MAC Cipher Feedback Code of Federal Regulations Complementary Metal Oxide Semiconductor Central Processing Unit Cyclic Redundancy Check Counter mode (encryption) Continuous Wave Digital to Analogue Converter Direct Memory Access Delta Sigma Modulator Electronic Code Book Evaluation Module Effective Number Of Bits USB Endpoint 0-5 Electro Static Discharge Equivalent Series Resistance European Telecommunications Standards Institute Federal Communications Commission FIFO and Frame Control First In First Out High Speed Serial Debug Inter-IC Sound Input / Output In-phase / Quadrature-phase Institute of Electrical and Electronics Engineers Intermediate Frequency I/O Controller
ISM ITU-T
Industrial, Scientific and Medical International Telecommunication Union - Telecommunication Standardization Sector Initialization Vector kilo bits per second 1024 bytes Linear Feedback Shift Register Low-Noise Amplifier Local Oscillator Link Quality Indication Least Significant Bit / Byte Message Authentication Code Micro Controller Unit Most Significant Byte Not Available Not Connected Output Feedback (encryption) Power Amplifier Printed Circuit Board Packet Error Rate Phase Locked Loop Power Mode 0-3 Power Management Controller Power On Reset Pulse Width Modulator Quad Leadless Package Random Access Memory Resolution Bandwidth RC Oscillator Radio Frequency Restriction on Hazardous Substances Receive Signal Strength Indicator Real-Time Clock Receive Serial Clock Start of Frame Delimiter Special Function Register Signal-to-noise and distortion ratio Start Of Frame Serial Peripheral Interface
IV kbps KB LFSR LNA LO LQI LSB MAC MCU MSB NA NC OFB PA PCB PER PLL PM{0-3} PMC POR PWM QLP RAM RBW RCOSC RF RoHS RSSI RTC RX SCK SFD SFR SINAD SOF SPI
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 5 of 252
CC2510FX / CC2511Fx
SRAM ST T/R TBD TX UART Static Random Access Memory Sleep Timer Transmit / Receive To Be Decided / To Be Defined Transmit Universal Asynchronous Receiver/Transmitter USB VCO VGA WDT XOSC USART Universal Synchronous/Asynchronous Receiver/Transmitter Universal Serial Bus Voltage Controlled Oscillator Variable Gain Amplifier Watchdog Timer Crystal Oscillator
2
References
[1]
NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/N.I.S.T., November 26, 2001. Available from the NIST website. http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
[2]
Universal Serial Bus Revision 2.0 Specification. Available from the USB Implementors Forum website. http://www.usb.org/developers/docs/
[3]
I2S bus specification, Philips Semiconductors, Available from the Philips Semiconductors website. http://www.semiconductors.philips.com/acrobat_download/various/I2SBUS.pdf
[4]
IEEE Std 1241-2000, IEEE standard for terminology and test methods for analog-to-digital converters.
3
Register conventions
Each SFR register is described in a separate table. The table heading is given in the following format: REGISTER NAME (SFR Address) - Register Description. Each RF register is described in a separate table. The table heading is given in the following format: XDATA Address: REGISTER NAME - Register Description All register descriptions include for each register bit a symbol denoted R/W describing the accessibility of the bit. The register values are always given in binary notation unless prefixed by `0x' which indicates hexadecimal notation.
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 6 of 252
CC2510FX / CC2511Fx
Symbol R/W R R0 R1 W W0 W1 H0 H1 Access Mode Read/write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 Hardware clear Hardware set
Table 1: Register bit conventions
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 7 of 252
CC2510FX / CC2511Fx
4
4.1 * * *
Features (continued from front page)
* High-Performance and Low-Power 8051-Compatible Microcontroller Optimized 8051 core which typically gives 8x the performance of a standard 8051 Dual data pointers In-circuit interactive debugging is supported for the IAR Embedded Workbench through a simple two-wire serial interface 8/16/32 kB Non-volatile Program Memory and 1/2/4 kB Data Memory 8, 16 or 32 kB of non-volatile Flash memory, in-system programmable through a simple two-wire interface or by the 8051 core Worst case flash memory endurance: 1000 write/erase cycles (applies per bit cell). Programmable read and write lock of portions of Flash memory for software security 1, 2 or 4 kB of internal SRAM Full-Speed USB Controller (CC2511Fx ) 5 bi-directional endpoints in addition to control endpoint 0 Full-Speed, 12 Mbps transfer rate. Support for Bulk, Isochronous endpoints Interrupt and * 4.7 * * 4.5 * * Support for expansion -law compression and
Typically used to connect to external DAC or ADC. Hardware AES Encryption/Decryption 128-bit AES coprocessor supported in hardware
4.6 * * * * * * *
Peripheral Features Powerful DMA Controller Power On Reset Battery monitor Eight channel, 8-14 bit ADC Programmable watchdog timer Real time clock with 32.768 kHz crystal oscillator Four timers: one general 16-bit timer, two general 8-bit timers, one MAC timer. The 16-bit timer can also be used in DeltaSigma Modulator (DSM) mode. This allows the timer to produce a high quality audio output signal that only requires a low-cost passive external filter. Two programmable USARTs master/slave SPI or UART operation for
4.2 *
*
*
* 4.3 * * * * * *
* *
Up to 21 configurable general-purpose digital I/O-pins (CC2511Fx has 19 generalpurpose digital I/O-pins) Random number generator Low Power Four flexible power modes for reduced power consumption Only 0.5 A current consumption in standby mode, where external interrupts or the real-time counter can wake up the system 0.3 A current consumption in power down mode, where external interrupts can wake up the system System can wake up on external interrupt or real-time counter event
1024 bytes of dedicated endpoint FIFO memory. 8 - 512 byte data packet size supported Configurable FIFO size for IN and OUT direction of endpoint I2S Interface Industry standard I2S interface for transfer of digital audio data Full duplex Mono and stereo support Configurable sample rate and sample size
4.4 * * * *
*
*
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 8 of 252
CC2510FX / CC2511Fx
* * Low-power fully static CMOS design System clock source can be 13 MHz RC oscillator or 26/48 MHz crystal oscillator. The 26/48 MHz oscillator is used when the radio is active. Optional clock source for ultra-low power operation can be either a low-power RC oscillator or an optional 32.768 kHz crystal oscillator Very fast transition from sleep modes to active enable ultra low average power consumption in low duty-cycle systems * 4.8 * * 2.4 GHz Radio with baseband modem Based on the industry leading CC2500 radio core Very few external components: Totally onchip frequency synthesizer, no external filters or RF switch needed Flexible support for packet oriented systems: On chip support for sync word detection, address check, flexible packet length and automatic CRC handling. * * * Supports use of DMA for both RX and TX. Resulting in minimal CPU interference even on high data rates. Programmable channel filter bandwidth 2-FSK, GFSK and MSK supported. Optional automatic whitening and dewhitening of data Support for asynchronous transparent receive/transmit mode for backwards compatibility with existing radio communication protocols Programmable Carrier Sense indicator Programmable Preamble Quality Indicator for detecting preambles and improved protection against sync word detection in random noise Support for automatic Clear Channel Assessment (CCA) before transmitting (for listen-before-talk systems) Support for per-package Link Quality Indication
* * * *
*
*
*
*
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 9 of 252
CC2510FX / CC2511Fx
5 Absolute Maximum Ratings
Under no circumstances must the absolute maximum ratings given in Table 2 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.
Parameter Supply voltage Voltage on any digital pin Input RF level Storage temperature range Solder reflow temperature -50 Min -0.3 -0.3 Max 3.6 VDD+0.3, max 3.6 +10 150 260 Units V V dBm C C Device not programmed According to IPC/JEDEC J-STD-020C Condition All supply pins must have the same voltage
Table 2: Absolute Maximum Ratings
Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.
6
6.1
Operating Conditions
CC2510FX Operating conditions
The operating conditions for CC2510FX are listed Table 3 in below.
Parameter Operating ambient temperature, TA Operating supply voltage Min -40 2.0 Max 85 3.6 Unit C V All supply pins must have the same voltage Condition
Table 3: Operating Conditions CC2510FX 6.2
CC2511Fx Operating conditions
The operating conditions for CC2511Fx are listed Table 4 in below.
Parameter Operating ambient temperature, TA Operating supply voltage Min 0 3.0 Max 80 3.6 Unit C V Condition
Table 4 Operating Conditions CC2511Fx
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 10 of 252
CC2510FX / CC2511Fx
7 Electrical Specifications
TA=25C, VDD=3.0V if nothing else stated. Measured on Chipcon's CC2510FX EM reference design.
Parameter Power On Reset Voltage Min Typ 1.1 Max Unit V Condition Monitors the unregulated supply
Current Consumption
MCU Active Mode, static MCU Active Mode, dynamic 500 270 7.5 mA 7.0 20 mA 18 18 mA 16 23 mA 21 A A/MHz Digital regulator on, High Speed RCOSC running. No radio, crystals, or peripherals. Digital regulator on, High Speed RCOSC running. No radio, crystals, or peripherals.
MCU Active Mode, highest speed
CC2510FX: MCU running at full speed (26 MHz), XOSC running. No peripherals. CC2511Fx: MCU running at full speed (24 MHz), XOSC
running. No peripherals.
MCU Active and RX Mode, -100 dBm input
CC2510FX: MCU running at full speed (26 MHz), XOSC running, radio in RX mode. No peripherals. CC2511Fx: MCU running at full speed (24 MHz), XOSC
running, radio in RX mode. No peripherals.
MCU Active and RX Mode, -30 dBm input
CC2510FX: MCU running at full speed (26 MHz), XOSC running, radio in RX mode. No peripherals. CC2511Fx: MCU running at full speed (24 MHz), XOSC
running, radio in RX mode. No peripherals.
MCU Active and TX Mode, 0dBm
CC2510FX: MCU running at full speed (26 MHz), XOSC running, radio in TX mode. No peripherals. CC2511Fx: MCU running at full speed (24 MHz), XOSC
running, radio in TX mode. No peripherals. Digital regulator on, High Speed RCOSC and crystal oscillator off. 32.768kHz XOSC, POR and ST active. RAM retention. Digital regulator off, High Speed RCOSC and crystal oscillator off. 32.768kHz XOSC, POR and ST active. RAM retention. No clocks. RAM retention. Power On Reset active. Add to the figures above if the peripheral unit is activated
Power mode 1
187
A
Power mode 2 Power mode 3
0.5 0.3
A A
Peripheral Current Consumption
Timer 1 Timer 2 Timer 3 Timer 4 Sleep Timer AES ADC USART1 / USART2 DMA Flash write 10 10 10 10 0.5 50 0.9 12 30 3 A/MHz A/MHz A/MHz A/MHz A A/MHz mA A/MHz A/MHz mA
When enabled When enabled When enabled When enabled Including low-power RC oscillator or 32.768kHz XOSC When encrypting/decrypting When converting For each USART in use. Not including current for driving I/O pins. When operating, not including current for memory access
Table 5: Electrical Specifications
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 11 of 252
CC2510FX / CC2511Fx
7.1 General Characteristics TA=25C, VDD=3.0V if nothing else stated.
Parameter Min Typ Max Unit Condition/Note
Wake-Up and Timing
PM1 PM0 31 ns Digital regulator on, High Speed RCOSC or crystal oscillator running. Entry from PM1 to PM0 takes one clock period. Digital regulator on, High Speed RCOSC and crystal oscillator off. Start-up of High Speed RCOSC. Digital regulator on. Crystal oscillator off. Start-up of Crystal oscillator and RF TX/RX begins. Digital regulator off, High Speed RCOSC and crystal oscillator off. Start-up of regulator and High Speed RCOSC.
PM1 PM1
PM0 PM0 RX/TX
10 195
13
s s s
PM2/PM3
PM0
50
Radio part
Frequency range Data rate 2400 1.2 1.2 26 2483.5 500 250 500 MHz kbps kbps kbps 2-FSK GFSK and OOK (Shaped) MSK (also known as differential offset QPSK) Optional Manchester encoding (halves the data rate).
Table 6: General Characteristics
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 12 of 252
CC2510FX / CC2511Fx
7.2 RF Receive Section TA=25C, VDD=3.0V if nothing else stated. Measured on Chipcon's CC2510FX EM reference design.
Parameter Digital channel filter bandwidth Min 58 Typ Max 812 Unit kHz Condition/Note User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0 MHz crystal).
2.4 kbps data rate, current optimized, MDMCFG2.DEM_DCFILT_OFF = 1 (2-FSK, 1% packet error rate, 20 bytes packet length, 203 kHz digital channel filter bandwidth) -105 Receiver sensitivity Saturation Adjacent channel rejection Alternate channel rejection -107 -13 23 31 dBm
CC2510FX: The typical current consumption is in this case 17.0 mA at sensitivity llimit. CC2511Fx: The typical current consumption is in this case 17.0 mA
at sensitivity llimit.
dBm dB dB Desired channel 3 dB above the sensitivity limit. 250 kHz channel spacing Desired channel 3 dB above the sensitivity limit. 250 kHz channel spacing See Figure 52 for plot of selectivity versus frequency offset
10 kbps data rate, current optimized, MDMCFG2.DEM_DCFILT_OFF = 1 (2-FSK, 1% packet error rate, 20 bytes packet length, 232 kHz digital channel filter bandwidth) Receiver sensitivity Saturation Adjacent channel rejection Alternate channel rejection -98 dBm The sensitivity can be improved to typically -100 dBm by setting MDMCFG2.DEM_DCFILT_OFF = 0 . The typical current consumption is in this case 17.3 mA at sensitivity llimit. Desired channel 3 dB above the sensitivity limit. 250 kHz channel spacing Desired channel 3 dB above the sensitivity limit. 250 kHz channel spacing See Figure 53 for plot of selectivity versus frequency offset 250 kbps data rate, MDMCFG2.DEM_DCFILT_OFF = 0 (MSK, 1% packet error rate, 20 bytes packet length, 600 kHz digital channel filter bandwidth) Receiver sensitivity Saturation Adjacent channel rejection Alternate channel rejection -91 -90 -13 21 30 dBm dBm dB dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing See Figure 54 for plot of selectivity versus frequency offset 250 kbps data rate current optimized, MDMCFG2.DEM_DCFILT_OFF = 1 (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver sensitivity Saturation Adjacent channel rejection Alternate channel rejection -86 -13 21 30 dBm dBm dB dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing See Figure 55 for plot of selectivity versus frequency offset 500 kbps data rate, MDMCFG2.DEM_DCFILT_OFF = 0 (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver sensitivity Saturation Adjacent channel rejection -81 -18 14 dBm dBm dB Desired channel 3 dB above the sensitivity limit. 1 MHz channel spacing
-9 18 25
dBm dB dB
CC2510FX CC2511Fx
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 13 of 252
CC2510FX / CC2511Fx
Parameter Alternate channel rejection General Selectivity at 10 MHz offset Selectivity at 20 MHz offset Selectivity at 50 MHz offset Spurious emissions 25 MHz - 1 GHz Above 1 GHz 47 52 54 dB dB dB Desired channel at -80 dBm. Compliant with ETSI EN 300 440 class 2 receiver requirements. Desired channel at -80 dBm. Compliant with ETSI EN 300 440 class 2 receiver requirements. Desired channel at -80 dBm. Compliant with ETSI EN 300 440 class 2 receiver requirements. Min Typ 25 Max Unit dB Condition/Note Desired channel 3 dB above the sensitivity limit. 1 MHz channel spacing See Figure 56 for plot of selectivity versus frequency offset
-57 -47
dBm dBm
Table 7: RF Receive Section 7.3 RF Transmit Section
TA=25C, VDD=3.0V if nothing else stated. Measured on Chipcon's CC2510FX EM reference design.
Parameter Differential load impedance Output power, highest setting Min Typ 80 + j74 +1 Max Unit Condition/Note Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC2510FX EM reference design available from Chipcon's website. Output power is programmable and is available across the entire frequency band Delivered to 50 single-ended load via Chipcon reference RF matching network. Output power, lowest setting -30 dBm Output power is programmable and is available across the entire frequency band Delivered to 50 single-ended load via Chipcon reference RF matching network. Spurious emissions 25 MHz - 1 GHz Above 1 GHz -57 -47 dBm dBm
dBm
Table 8: RF Transmit Parameters
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 14 of 252
CC2510FX / CC2511Fx
7.4 7.4.1 26/48 MHz Crystal Oscillator
CC2510 Crystal Oscillator (26 MHz)
TA=25C, VDD=3.0V if nothing else is stated.
Parameter Crystal frequency Crystal frequency accuracy requirement Min 24 Typ 26 40 Max 27 Unit MHz ppm This is the total tolerance including a) initial tolerance, b) ageing and c) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. 1 10 6 212 5 13 7 20 100 pF pF us Condition/Note
Crystal shunt cap Load capacitance ESR Start-up time
Table 9: 26 MHz Crystal Oscillator Parameters (CC2510)
7.4.2
CC2511Fx Crystal Oscillator (48 MHz)
TA=25C, VDD=3.0V if nothing else is stated.
Parameter Crystal frequency Crystal frequency accuracy requirement Min 48 Typ 48 40 Max 48 Unit MHz ppm This is the total tolerance including a) initial tolerance, b) ageing and c) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. 2 12 3 13 30 628 7 14 60 pF pF us Condition/Note
Crystal shunt cap Load capacitance ESR Start-up time
Table 10: 48 MHz Crystal Oscillator Parameters (CC2511Fx) 7.5 32.768 kHz Crystal Oscillator
TA =25C, VDD=3.0V if nothing else is stated.
Parameter Crystal frequency Crystal frequency accuracy requirement ESR Crystal shunt cap Load capacitance Start-up time 40 0.9 12 130 2.0 16 450 Min Typ 32.768 Max Unit kHz ppm Condition/Note
pF pF ms
Table 11: 32.768 kHz Crystal Oscillator Parameters
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 15 of 252
CC2510FX / CC2511Fx
7.6 Low Power RC Oscillator TA=25C, VDD=3.0V if nothing else is stated.
Parameter Calibrated frequency Frequency accuracy after calibration Temperature coefficient Supply voltage coefficient Initial calibration time +0.4 +3 2 Min 34.6 Typ 34.7 Max 36 +0.3 -10 Unit kHz % % / C %/V ms Frequency drift when temperature changes after calibration Frequency drift when supply voltage changes after calibration When the RC Oscillator is enabled, calibration is continuously done in the background as long as the crystal oscillator is running. Programmable, dependent on XTAL frequency Condition/Note Calibrated RC Oscillator frequency is XTAL frequency divided by 750
Wake-up period
58
59650
Seconds
Table 12: Low Power RC Oscillator parameters 7.7 High Speed RC Oscillator
TA=25C, VDD=3.0V if nothing else is stated.
Parameter Frequency Uncalibrated frequency accuracy Calibrated frequency accuracy Start-up time Temperature coefficient Supply voltage coefficient Initial calibration time 50 Min Typ 13 15 1 10 -325 28 Max Unit MHz % % s ppm / C ppm / V s Frequency drift when temperature changes after calibration Frequency drift when supply voltage changes after calibration When the High Speed RC Oscillator is enabled, calibration is continuously done in the background as long as the crystal oscillator is running. Condition/Note Calibrated High Speed RC Oscillator frequency is XTAL frequency multiplied by 1/2
Table 13: High Speed RC Oscillator parameters
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
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CC2510FX / CC2511Fx
7.8 Frequency Synthesizer Characteristics
TA=25C, VDD=3.0V if nothing else stated. Measured on Chipcon's CC2510FX EM reference design.
Parameter Programmed frequency resolution Synthesizer frequency tolerance RF carrier phase noise RF carrier phase noise RF carrier phase noise RF carrier phase noise RF carrier phase noise RF carrier phase noise RF carrier phase noise RF carrier phase noise PLL turn-on / hop time Min 397 Typ FXOSC/ 16 2 40 Max 412 Unit Hz ppm Condition/Note 26-27 MHz crystal. Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing. @ 50 kHz offset from carrier @ 100 kHz offset from carrier @ 200 kHz offset from carrier @ 500 kHz offset from carrier @ 1 MHz offset from carrier @ 2 MHz offset from carrier @ 5 MHz offset from carrier @ 10 MHz offset from carrier Time from leaving the IDLE state until arriving in the RX, FSTXON or TX state, when not performing calibration. Crystal oscillator running. Settling time for the 1xIF frequency step from RX to TX, and vice versa. Calibration can be initiated manually, or automatically before entering or after leaving RX/TX. Min/typ/max time is for 27/26/26 MHz crystal frequency.
-78 -78 -81 -90 -100 -108 -116 -127 90
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz s
PLL RX/TX and TX/RX settling time PLL calibration time 0.69
10 18739 0.72 0.72
s XOSC cycles ms
Table 14: Frequency Synthesizer Parameters 7.9 Analog Temperature Sensor
TA=25C, VDD=3.0V if nothing else stated. Measured on Chipcon's CC2510FX EM reference design.
Parameter Output voltage at -40C Output voltage at 0C Output voltage at +40C Output voltage at +80C Output voltage at +120C Temperature coefficient Error in calculated temperature, calibrated Current consumption increase when enabled Min Typ 0.660 0.755 0.859 0.958 1.056 2.54 2 0.3 Max Unit V V V V V mV/C C mA Fitted from -20C to +80C From -20C to +80C when using 2.54mV / C, after 1-point calibration at room temperature Condition/Note
Table 15: Analog Temperature Sensor Parameters
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
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CC2510FX / CC2511Fx
7.10 8-14 bit ADC TA=25C, VDD=3.0V if nothing else stated. The numbers given here are based on tests performed in accordance to the IEEE Std 1241-2000 [4].
Parameter Input voltage External reference voltage External reference voltage differential Number of bits (ENOB) Min 0 0 0 7 Typ Max AVDD AVDD AVDD 13 Unit V V V bits Condition/Note AVDD is voltage on AVDD pin AVDD is voltage on AVDD pin AVDD is voltage on AVDD pin The ADC is a delta-sigma. Effective resolution depends on sample rate used. Differential input signal and reference assumed. Offset 18 20 0.3
3
-
122 132
Offset should be measured by sampling internal 1 AGND . s LSB LSB dB dB dB dB
Conversion time Differential nonlinearity 3 (DNL) Integral nonlinearity (INL) SINAD
23
CC2510 using 26 MHz system clock. CC2511Fx using 24 MHz system clock.
8-bits setting 8-bits setting 8-bits setting 10-bits setting 12-bits setting 14-bits setting
0.8 45 56 66 75
(sine input)
Table 16: 8-14 bit ADC Characteristics
The offset value depends on several factors as: mode of operation, temperature, voltage, noise, reference etc. In order to sample with high accuracy, the DC value of internal AGND and AVDD should be measured before starting the wanted sampling sequence. Thus, knowing the statistical nonlinearity and effective number of bits, the correct sample value can easily be calculated.
2 3
1
The calculation assumes a differential input signal and a correlated differential reference.
DNL, INL and SINAD are measured using dynamic characterisation methods by applying a sine wave input at P0.0 with AVDD_SOC as reference.
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
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CC2510FX / CC2511Fx
7.11 Control AC Characteristics TA=85C, VDD=3.0V if nothing else stated. Measured on Chipcon's CC2510FX EM reference design.
Parameter Min Typ Max 26 System clock, fSYSCLK tSYSCLK= 1/ fSYSCLK 24 24 MHz Unit MHz Condition/Note
CC2510FX: Applies when 26 MHz crystal oscillator is used. Maximum system clock is 13 MHz when high speed RC oscillator is used. CC2511Fx: Applies when 48 MHz crystal oscillator is used.
Maximum system clock is 13 MHz when high speed RC oscillator is used.
RESET_N low width Interrupt pulse width
2.5 tSYSCLK
ns
See item 1, Figure 1. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. See item 2, Figure 1.This is the shortest pulse that is guaranteed to be recognized as an interrupt request. In PM2/3 the internal synchronizers are bypassed so this requirement does not apply in PM2/3.
Table 17: Control Inputs AC Characteristics
1 RESET_N
Px.n
2
2
Px.n
Figure 1: Control Inputs AC Characteristics
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 19 of 252
CC2510FX / CC2511Fx
7.12 SPI AC Characteristics TA=85C, VDD=3.0V if nothing else stated. Measured on Chipcon's CC2510FX EM reference design.
Parameter SCK period Min Typ See section 13.13.3 50% 2*tSYSCLK 30 10 10 25 100 50% 10 10 25 ns ns ns ns ns ns ns ns Max Unit ns Condition/Note Master. See item 1 Figure 2
SCK duty cycle SSN low to SCK SCK to SSN high MISO setup MISO hold SCK to MOSI SCK period SCK duty cycle MOSI setup MOSI hold SCK to MISO
Master. See item 5 Figure 2 See item 6 Figure 2 Master. See item 2 Figure 2 Master. See item 3 Figure 2 Master. See item 4 Figure 2, load = 10 pF Slave. See item 1 Figure 2 Slave. Slave. See item 2 Figure 2 Slave. See item 3 Figure 2 Slave. See item 4 Figure 2, load = 10 pF
Table 18: SPI AC Characteristics
Figure 2: SPI AC Characteristics
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
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CC2510FX / CC2511Fx
7.13 Debug Interface AC Characteristics TA=85C, VDD=3.0V if nothing else stated. Measured on Chipcon's CC2510FX EM reference design.
Parameter Debug clock period Debug data setup Debug data hold Clock to data delay RESET_N inactive after P2_2 rising 10 Min 31.25 5 5 10 Typ Max Unit ns Condition/Note See item 1 Figure 3 See item 2 Figure 3 See item 3 Figure 3 See item 4 Figure 3, load = 10 pF See item 5 Figure 3
Table 19: Debug Interface AC Characteristics
1 DEBUG CLK P2_2
3
2 DEBUG DATA P2_1 4
DEBUG DATA P2_1
RESET_N
5
Figure 3: Debug Interface AC Characteristics 7.14 Port Outputs AC Characteristics TA=85C, VDD=3.0V if nothing else stated. Measured on Chipcon's CC2510FX EM reference design.
Parameter P0, P1, P2Port output pins, rise and fall time Min Typ 10 Max Unit Condition/Note Load = 10 pF Timing is with respect to 10% VDD and 90% VDD levels.
Table 20: Port Outputs AC Characteristics
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
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CC2510FX / CC2511Fx
7.15 Timer Inputs AC Characteristics TA =85C, VDD=3.0V if nothing else stated. Measured on Chipcon's CC2510FX EM reference design.
Parameter Input capture pulse width Min tSYSCLK Typ Max Unit Condition/Note Synchronizers determine the shortest input pulse that can be recognized. The synchronizers operate from the current system clock rate
Table 21: Timer Inputs AC Characteristics
7.16 DC Characteristics The DC Characteristics of CC2510FX/CC2511Fx are listed in Table 22 below. TA=25C, VDD=3.0V if nothing else stated. Measured on Chipcon's CC2510FX EM reference design.
Digital Inputs/Outputs Logic "0" input voltage Logic "1" input voltage Logic "0" output voltage Logic "1" output voltage Logic "0" input current Logic "1" input current I/O pin pull-up and pull-down resistor Min 0 VDD-0.25 0 VDD-0.25 N/A N/A 17 Typ 0.7 VDD 0 VDD -1 1 20 Max 0.9 VDD 0.25 VDD -1 1 23 Unit V V V V A A k For up to 4mA output current on all pins except P1_0 and P1_1 which are up to 20 mA For up to 4mA output current on all pins except P1_0 and P1_1 which are up to 20 mA Input equals 0V Input equals VDD Condition
Table 22: DC Characteristics
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 22 of 252
CC2510FX / CC2511Fx
8 Pin and I/O Port Configuration
The CC2510FX pinout is shown in Figure 4 and Table 23. See section 13.1 for details on the configuration of digital I/O ports.
AVDD_DREG
RESET_N
DCOUPL
36 35 34 33 32 31 30 29 28
P1_2 1 DVDD 2 P1_1 3 P1_0 4 P0_0 5 P0_1 6 P0_2 7 P0_3 8 P0_4 9
GUARD
P1_3
P1_4
P1_5
P1_6
P1_7
27 RBIAS 26 AVDD 25 AVDD 24 RF_N 23 RF_P 22 AVDD 21 XOSC_Q1 20 XOSC_Q2 19 AVDD 10 11 12 13 14 15 16 17 18
DVDD P0_5 P0_6 P0_7 P2_0 P2_1 P2_2 P2_3/XSOC32_Q1 P2_4/XOSC32_Q2
AGND Exposed die attached pad
Figure 4: CC2510FX Pinout top view Note: The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip.
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 23 of 252
CC2510FX / CC2511Fx
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name GND P1_2 DVDD P1_1 P1_0 P0_0 P0_1 P0_2 P0_3 P0_4 DVDD P0_5 P0_6 P0_7 P2_0 P2_1 P2_2 Pin type Ground D I/O Power (Digital) D I/O D I/O D I/O D I/O D I/O D I/O D I/O Power (Digital) D I/O D I/O D I/O D I/O D I/O D I/O Description The exposed die attach pad must be connected to a solid ground plane Port 1.2 2.0V-3.6V digital power supply for digital I/O Port 1.1 Port 1.0 Port 0.0 Port 0.1 Port 0.2 Port 0.3 Port 0.4 2.0V-3.6V digital power supply for digital I/O Port 0.5 Port 0.6 Port 0.7 Port 2.0 Port 2.1 Port 2.2 17 18 19 20 21 22 23 P2_3/XOSC32_Q1 P2_4/XOSC32_Q2 AVDD XOSC_Q2 XOSC_Q1 AVDD RF_P D I/O D I/O Power (Analog) Analog I/O Analog I/O Power (Analog) RF I/O Port 2.3/32.768 kHz crystal oscillator pin 1 Port 2.4/32.768 kHz crystal oscillator pin 2 2.0V-3.6V analog power supply connection 26 MHz crystal oscillator pin 2 26 MHz crystal oscillator pin 1, or external clock input 2.0V-3.6V analog power supply connection Positive RF input signal to LNA in receive mode Positive RF output signal from PA in transmit mode 24 RF_N RF I/O Negative RF input signal to LNA in receive mode Negative RF output signal from PA in transmit mode 25 26 27 28 29 30 31 32 33 34 35 36 AVDD AVDD RBIAS GUARD AVDD_DREG DCOUPL RESET_N P1_7 P1_6 P1_5 P1_4 P1_3 Power (Analog) Power (Analog) Analog I/O Power (Digital) Power (Digital) Power decoupling DI D I/O D I/O D I/O D I/O D I/O 2.0V-3.6V analog power supply connection 2.0V-3.6V analog power supply connection External precision bias resistor for reference current Power supply connection for digital noise isolation 2.0V-3.6V digital power supply for digital core voltage regulator 1.8V digital power supply decoupling Reset, active low Port 1.7 Port 1.6 Port 1.5 Port 1.4 Port 1.3
Table 23: CC2510FX Pinout overview
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 24 of 252
CC2510FX / CC2511Fx
The CC2511Fx pinout is shown in Figure 5 and Table 24. See section 13.1 for details on the configuration of digital I/O ports.
AVDD_DREG
RESET_N
DCOUPL
36 35 34 33 32 31 30 29 28
P1_2 1 DVDD 2 P1_1 3 P1_0 4 P0_0 5 P0_1 6 P0_2 7 P0_3 8 P0_4 9
GUARD
P1_3
P1_4
P1_5
P1_6
P1_7
27 R_BIAS 26 AVDD 25 AVDD 24 RF_N 23 RF_P 22 AVDD 21 XOSC_Q1 20 XOSC_Q2 19 AVDD 10 11 12 13 14 15 16 17 18
DM P2_3/XSOC32_Q1 P2_4/XOSC32_Q2 DP P0_5 P2_0 P2_1 P2_2 DVDD
AGND Exposed die attached pad
Figure 5: CC2511Fx Pinout top view Note: The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip.
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 25 of 252
CC2510FX / CC2511Fx
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pin name GND P1_2 DVDD P1_1 P1_0 P0_0 P0_1 P0_2 P0_3 P0_4 DP DM DVDD P0_5 P2_0 P2_1 P2_2 P2_3/XOSC32_Q1 P2_4/XOSC32_Q2 AVDD XOSC_Q2 XOSC_Q1 AVDD RF_P Pin type Ground D I/O Power (Digital) D I/O D I/O D I/O D I/O D I/O D I/O D I/O USB I/O USB I/O Power (Digital) D I/O D I/O D I/O D I/O D I/O D I/O Power (Analog) Analog I/O Analog I/O Power (Analog) RF I/O Description The exposed die attach pad must be connected to a solid ground plane Port 1.2 2.0V-3.6V digital power supply for digital I/O Port 1.1 Port 1.0 Port 0.0 Port 0.1 Port 0.2 Port 0.3 Port 0.4 USB Differential Data Bus Plus USB Differential Data Bus Minus 2.0V-3.6V digital power supply for digital I/O Port 0.5 Port 2.0 Port 2.1 Port 2.2 Port 2.3/32.768 kHz crystal oscillator pin 1 Port 2.4/32.768 kHz crystal oscillator pin 2 2.0V-3.6V analog power supply connection 48 MHz crystal oscillator pin 2 48 MHz crystal oscillator pin 1, or external clock input 2.0V-3.6V analog power supply connection Positive RF input signal to LNA in receive mode Positive RF output signal from PA in transmit mode 24 RF_N RF I/O Negative RF input signal to LNA in receive mode Negative RF output signal from PA in transmit mode 25 26 27 28 29 30 31 32 33 34 35 36 AVDD AVDD RBIAS GUARD AVDD_DREG DCOUPL RESET_N P1_7 P1_6 P1_5 P1_4 P1_3 Power (Analog) Power (Analog) Analog I/O Power (Digital) Power (Digital) Power decoupling DI D I/O D I/O D I/O D I/O D I/O 2.0V-3.6V analog power supply connection 2.0V-3.6V analog power supply connection External precision bias resistor for reference current Power supply connection for digital noise isolation 2.0V-3.6V digital power supply for digital core voltage regulator 1.8V digital power supply decoupling Reset, active low Port 1.7 Port 1.6 Port 1.5 Port 1.4 Port 1.3
Table 24: CC2511Fx Pinout overview
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 26 of 252
CC2510FX / CC2511Fx
9 Circuit Description
Figure 6: CC2510FX/CC2511Fx Block Diagram
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 27 of 252
CC2510FX / CC2511Fx
A block diagram of CC2510FX/CC2511Fx is shown in Figure 6. The modules can be roughly divided into one out of three categories: CPUrelated modules, radio-related modules and modules related to power, test and clock distribution. In the following subsections, a short description of each module that appears in Figure 6 is given. 9.1 CPU and Peripherals priority, transfer mode, addressing mode, source and destination pointers, and transfer count) with DMA descriptors anywhere in memory. Many of the hardware peripherals rely on the DMA controller for efficient operation (AES core, flash controller, USARTs, Timers and ADC interface) by performing data transfers between a single SFR address and flash/SRAM. See section 13.2 for details. The interrupt controller services 18 interrupt sources, divided into six interrupt groups, each of which is associated with one out of four interrupt priorities. An interrupt request is serviced even if the device is in a sleep mode (power modes 1-3) by bringing the CC2510FX/CC2511Fx back to active mode (power mode 0). The debug interface implements a proprietary two-wire serial interface that is used for incircuit debugging. Through this debug interface it is possible to perform an erasure of the entire flash memory, control which oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051 core, set code breakpoints, and single step through instructions in the code. Using these techniques, it is possible to elegantly perform in-circuit debugging and external flash programming. See section 12.9 for details. The I/O-controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral modules control certain pins or whether they are under software control. If uses as I/O whether each pin is configured as an input or output, and if a pull-up or pull-down resistor in the pad is connected. Each peripheral that connects to the I/O-pins can choose between two different locations to ensure flexibility in various applications. See section 13.1 for details. The sleep timer is an ultra-low power timer that counts 32.768 kHz crystal oscillator or 32 34.6667 kHz RC oscillator periods. The sleep timer runs continuously in all operating modes except power mode 3. It can be configured in one of several resolution modes, to strike the right balance between timer resolution and timeout period. Typical uses for it is as a realtime counter that runs regardless of operating mode (except power mode 3) or as a wakeup timer to get out of power modes 1 or 2. See section 13.5 for details.
The 8051 CPU core is a single-cycle 8051compatible core. It has three different memory access buses (SFR, DATA and CODE/XDATA), a debug interface and an 18input extended interrupt unit. See section 12 for details. The memory crossbar/arbitrator is at the heart of the system as it connects the CPU and DMA controller with the physical memories and all peripherals through the SFR bus. The memory arbitrator has four memory access points, which can access three physical memories: a 1/2/4 KB SRAM, 8/16/32 KB flash memory or SFR registers. The memory arbitrator is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same physical memory. The SFR bus is drawn conceptually in the block diagram as a common bus that connects all hardware peripherals to the memory arbitrator. The SFR bus also provides access to the radio registers in the radio register bank even though these are indeed mapped into XDATA memory space. The 1/2/4 KB SRAM maps to the DATA memory space and part of the XDATA/CODE memory spaces. The memory is an ultra-lowpower SRAM that retains its contents even when the digital part is powered off (power modes 2 and 3). The 8/16/32 KB flash block provides in-circuit programmable non-volatile program memory for the device and maps into the CODE and XDATA memory spaces. Writing to the flash block is performed through a flash controller that allows page-wise (1024 byte) erasure and byte-wise reprogramming. See section 13.16 for details. A versatile five-channel DMA controller is available in the system. It accesses memory using a unified memory space (XDATA) and has therefore access to all physical memories. Each channel is configured (trigger event,
CC2510FX/CC2511Fx to reset itself in case the
A
built-in
watchdog
timer
allows
the
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 28 of 252
CC2510FX / CC2511Fx
firmware hangs. When enabled, the watchdog timer must be cleared periodically, otherwise it will reset the device when it times out. See section 13.12 for details. Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period value and three individually programmable counter/capture channels each with a 16-bit compare value. Each of the counter/capture channels can be used as PWM outputs or to capture the timing of edges on input signals. A second order Sigma-Delta noise shaper mode is also supported for audio applications. See section 13.3 for details. Timer 2 (MAC timer) is specially designed to support time-slotted protocols in software. The timer has a configurable timer period and 18bit tunable prescaler range. See section 13.4 for details. Timers 3 and 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler, an 8-bit period value and one programmable counter/capture channel with an 8-bit compare value. Each of the counter/capture channels can be used as PWM outputs or to capture the timing of edges on input signals. See section Error! Reference source not found. for details. USART 0 and 1 are each configurable as either an SPI master/slave or a UART. They provide double buffering on both RX and TX to support high-throughput full-duplex applications. Each has its own high-precision baud-rate generator thus leaving the ordinary timers free for other uses. See section 13.13 for details. The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with 128-bit keys. See section 13.9 for details. The ADC supports 8 to 14 bits of resolution in a 30 kHz to 4 kHz bandwidth respectively. DC and audio conversion with up to eight input channels (Port 0) is possible. The inputs can be selected as single ended or differential. The reference voltage can be internal, AVDD, or a single ended or differential external signal. The ADC also has a temperature sensor input channel. The ADC can automate the process of periodic sampling or conversion over a sequence of channels. See Section 13.7 for details. The USB allows the CC2511Fx to implement a Full-Speed USB 2.0 compatible device. The USB has a dedicated 1 KB SRAM that is used for the endpoint FIFOs. 5 endpoints are available in addition to control endpoint 0. Each of these endpoints must be configured as Bulk/Interrupt or Isochronous and can be used as IN, OUT or IN/OUT. Double buffering of packets is also supported for endpoints 1-5. The maximum FIFO memory available for each endpoint is as follows: 32 bytes for endpoint 0, 32 bytes for endpoint 1, 64 bytes for endpoint 2, 128 bytes for endpoint 3, 256 bytes for endpoint 4 and 512 bytes for endpoint 5. When an endpoint is used as IN/OUT the FIFO memory available for the endpoint can be distributed between IN and OUT depending on the demands of the application. The USB does not exist on the CC2510FX. See section 13.15 for details. The I2S can be used to send/receive audio samples to/from an external sound processor or DAC and may operate at full or half duplex. Samples of up to 16-bits resolution can be used although the I2S can be configured to send more low order bits if necessary to be compliant with the resolution of the receiver. (up to 32 bit) The maximum bit-rate supported is 3.5 Mbps. The I2S can be configured as a master or slave device and supports both mono and stereo. Automatic -Law expansion and compression can also be configured. See section 13.14 on page 158 for details. 9.2 Radio
CC2510FX/CC2511Fx features an RF transceiver based on the industry-leading CC2500,
requiring very few external components. See Section 15 for details.
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 29 of 252
CC2510FX / CC2511Fx
10 Power Control
The CC2510FX/CC2511Fx has four power modes, called PM0, PM1, PM2 and PM3. PM0 is the active mode while PM3 has the lowest power consumption. The power modes are shown in Table 25 together with voltage regulator and oscillator options. PM1: The voltage regulator to the digital part is on. Neither the 26/48 MHz crystal oscillator nor the high speed RC oscillator is running. Either the low power RC oscillator or the 32.768 kHz crystal oscillator is running. The system will go to PM0 on reset or an external interrupt or when the sleep timer expires. PM2: The voltage regulator to the digital core is turned off. Neither the 26/48 MHz crystal oscillator nor the high speed RC oscillator is running. Either the low power RC oscillator or the 32.768 kHz crystal oscillator is running. The system will go to PM0 on reset or an external interrupt or when the sleep timer expires. The CC2511Fx will lose all USB state information when PM2 is entered. Thus, PM2 should not be used with USB. PM3: The voltage regulator to the digital core is turned off. None of the oscillators are running. The system will go to PM0 on reset or an external interrupt. The CC2511Fx will lose all USB state information when PM3 is entered. Thus, PM3 should not be used with USB.
Power Mode
High speed oscillator A None 26/48 MHz XOSC HS RCOSC
Low-speed oscillator A B None Low power RCOSC 32.768 kHz XOSC
Voltage regulator (digital)
Configuration
B
C
C
PM0 PM1 PM2 PM3
B, C A A A
B, C B, C B, C A
On On Off Off
Table 25: Power modes PM0: The full functional mode. The voltage regulator to the digital core is on and either the high speed RC oscillator or the 26/48 MHz crystal oscillator or both are running. Either the low power RC oscillator or the 32.768 kHz crystal oscillator is running.
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
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CC2510FX / CC2511Fx
11 Application Circuit
This section describes the recommended application circuit for the RF part of the CC2510FX/CC2511Fx, together with crystal oscillator connections and USB. Only a few external components are required CC2510FX/CC2511Fx RF for using the transceiver. The recommended application circuit for CC2510FX is shown in Figure 7. The recommended application circuits for CC2511Fx are shown in Figure 8 and Figure 9. The first circuit uses a fundamental crystal and the second uses a 3rd overtone crystal. The external components are described in Table 26, and typical values are given in Table 27. Notice that all application circuits are shown excluding supply decoupling capacitors and digital I/O. 11.1 Bias resistor The bias resistor R271 is used to set an accurate bias current. It is very important to use the specified tolerance for this resistor. 11.2 Balun and RF matching C232, C242, L231 and L241 form the recommended balun that converts the differential RF port on CC2510FX/CC2511Fx to a single-ended RF signal. (C241 and C231 are also needed for DC blocking). Together with an appropriate LC network, the balun components also transform the impedance to match a 50 antenna (or cable). Component values for the RF balun and LC network are easily found using the SmartRF(R) Studio software. Suggested values are listed in Table 27. The balun and LC filter component values and their placement are important to keep the performance optimized. It is recommended to follow the CC2510EM / CC2511Dongle reference design. 11.4 USB (CC2511Fx) For the CC2511Fx the DP and DM pins need series resistors R262 and R263 for impedance matching and the DP line must have a pull-up resistor, R264. The series resistors should match the 90 +/- 5% characteristic impedance of the USB bus. Notice that the pull-up resistor must be tied to a voltage source between 3.0 and 3.6 V (typically 3.3V). The voltage source must be derived from or controlled by the VBUS power supply, provided by the USB cable, such that when VBUS is removed, the pull-up resistor does not provide current to the D+ line. The pull-up resistor may be connected direcly between VBUS and the D+ line. Or if the CC2511Fx firmware need the ability to disconnect from the USB bus,, a I/O pin on the CC2511Fx can be used to control the pull-up resistor. 11.5 Power supply decoupling The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance. Chipcon provides a reference design that should be followed closely. The CC2511Fx should use a 48 MHz fundamental (X3) or a 48 MHz 3rd overtone low cost external crystal (X4). Depending on the option selected, different loading capacitors (C203, C214) or (C202, C212, C213) must be used. When X4 is used, an inductor, L281, must also be connected in series with C212. The circuit also shows the connections for the optional 32.768 kHz crystal oscillator, with external crystal X2 and loading capacitors C181 and C171. This crystal oscillator is used by the Sleep Timer providing a real-time clock function and is not required for radio operation. The sleep timer may use the internal RC oscillator as an alternative to X2. The internal RC oscillator is less accurate but saves cost and board space. When not using X2 P2_3 and P2_4 may be used as general IO pins.
11.3 Crystal The crystal oscillator for the CC2510FX uses an external crystal X1, with two loading capacitors (C201 and C211). See section 14 on page 190 for details.
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
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CC2510FX / CC2511Fx
Figure 7: Application Circuit for CC2510FX
Figure 8: Application Circuit for CC2511Fx with USB and fundamental crystal
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CC2510FX / CC2511Fx
Figure 9: Application Circuit for CC2511Fx with USB and 3rd overtone crystal
Component C301 C203/C214 C202/C212/C213 C201/C211 C231/C241 C232/C241 C233/C234 C181/C171 L231/L241 L232 L281 R271 R264 R262/R263 X1 X2 X3 X4
Description Decoupling capacitor for on-chip voltage regulator to digital part Crystal loading capacitors (fundamental crystal) Crystal loading capacitors (3 overtone crystal) Crystal loading capacitors, see section 14 on page 190 for details RF balun DC blocking capacitors RF balun/matching capacitors RF LC filter/matching capacitors Crystal loading capacitors if X2 is used. RF balun/matching inductors (inexpensive multi-layer type) RF LC filter inductor (inexpensive multi-layer type) Crystal inductor 56 k resistor for internal bias current reference, 1% tolerance D+ Pullup resistor D+ / D- series resistors for impedance matching 26 MHz -27 MHz crystal, see section 14 on page 190 for details 32.768 kHz crystal, optional 48 MHz crystal (fundamental) 48 MHz crystal (3 overtone)
rd rd
Table 26: Overview of external components (excluding supply decoupling capacitors)
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Component C301 C203/C214 C202 C212 C213 C201, C211 C231, C241 C171, C181 C232, C242 C233 C234 L231, L232, L241 L281 R271 R264 R262/R263 X1 X2 X3 X4
Value 100 nF10%, 0402 X5R 33 pF 56 pF 10 nF 33 pF 27 pF5%, 0402 NP0 100 pF5%, 0402 NP0 15 pF5%, 0402 NP0 1.0 pF0.25 pF, 0402 NP0 1.8 pF0.25 pF, 0402 NP0 1.5 pF0.25 pF, 0402 NP0 1.2 nH0.3 nH, 0402 monolithic, Murata LQG-15 series 470 nH10%, Murata LQM18NNR47K00 56 k1%, 0402 1.5 k5%
26.0 MHz surface mount crystal 32.768 kHz surface mount crystal (optional) 48.0 MHz surface mount crystal (fundamental) 48.0 MHz surface mount crystal (3 overtone)
rd
Table 27: Bill Of Materials for the CC2510FX/CC2511Fx application circuits (subject to changes)
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CC2510FX / CC2511Fx
12 8051 CPU
This section describes the 8051 CPU core, with interrupts, memory and instruction set. 12.1 8051 CPU Introduction The CC2510FX/CC2511Fx includes an 8-bit CPU core, which is an enhanced version of the industry standard 8051 core. The enhanced 8051 core uses the standard 8051 instruction set. Instructions execute faster than the standard 8051 due to the following: * One clock per instruction cycle is used as opposed to 12 clocks per instruction cycle in the standard 8051. Redundant bus states are eliminated. Parallel execution of fetch and execute phases. equivalent. However, because the 8051 core uses a different instruction timing than many other 8051 variants, existing code with timing loops may require modification. Also, because the peripheral units such as timers and serial ports differ from those on other 8051 cores, code which includes instructions using the peripheral units SFRs will not work correctly. 12.2 Reset The CC2510FX/CC2511Fx has three reset sources. The following events generate a reset: * * * Forcing RESET_N input pin low A power-on reset condition Watchdog timer reset condition
* *
Since an instruction cycle is aligned with memory fetch when possible, most of the single byte instructions are performed in a single clock cycle. In addition to the speed improvement, the enhanced 8051 core also includes architectural enhancements: * * Dual data pointers Extended 18-source interrupt unit
The initial conditions after a reset are as follows: * * I/O pins are configured as inputs with pull-up, except P1_0 and P1_1. CPU program counter is loaded with 0x0000 and program execution starts at this address All peripheral registers are initialized to their reset values (refer to register descriptions) Watchdog timer is disabled
*
The 8051 core is object code compatible with the industry standard 8051 microcontroller. That is, object code compiled with an industry standard 8051 compiler or assembler executes on the 8051 core and is functionally 12.3 Memory The 8051 CPU has four different memory spaces: CODE. A 16-bit read-only memory space for program memory. DATA. An 8-bit read/write data memory space, which can be directly or indirectly accessed by a single CPU instruction. The lower 128 bytes of the DATA memory space can be addressed either directly or indirectly, the upper 128 bytes only indirectly. XDATA. A 16-bit read/write data memory space access to which usually requires 4-5 CPU instruction cycles. Access to XDATA memory is also slower in hardware than DATA access as the CODE and XDATA memory spaces share a common bus on the CPU core
*
and instruction pre-fetch from CODE can thus not be performed in parallel with XDATA accesses. SFR. A 7-bit read/write register memory space, which can be directly accessed by a single CPU instruction. For SFR registers whose address is divisible by eight, each bit is also individually addressable. The four different memory spaces are distinct in the 8051 architecture, but are partly overlapping in the CC2510FX/CC2511Fx to ease DMA transfers and hardware debugger operation. How the different memory spaces are mapped onto the three physical memories (8/16/32 KB flash program memory, 1/2/4 KB SRAM and
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hardware registers) is described in section 12.3.1 Memory Map This section gives an overview of the memory map. The memory differs from the standard 8051 memory map in two important aspects, as described below. First, all the physical memories CODE, DATA, XDATA, radio register, USB registers and most of the hardware SFR registers are mapped into a unified XDATA memory space as shown in Figure 10. Note that 128 upper bytes of DATA are located at a different XDATA location than the SFR registers and they can be accessed directly. Mapping all the memory spaces to XDATA is primarily done to allow the DMA controller access them, thus allowing DMA transfers between these areas. This also means that any MCU operation that read/write or manipulate a XDATA variable can be used on the entire unified XDATA memory space, except writing to or changing data in the 8/16/32 KB CODE memory space (FLASH). The hardware SFR register shown in gray in Table 29 are not mapped into the XDATA memory space, thus they can not be accessed from the DMA. Secondly, the CODE memory space is mapped identically to the XDATA. See Figure 10. This is primarily to done to allow program execution out of the SRAM/XDATA. Details about the mapping of all 8051 memory spaces are given in the next section. 12.3.2.
0xFF 0x00
DATA memory space
0xFFFF 0xFF00 0xFEFF
Fast access RAM Slow access RAM / program memory in RAM Unimplemented Hardware registers Unimplemented USB registers ( Unimplemented )
4 kB SRAM
0xFF 0x80
SFR memory space
0xF000 0xEFFF 0xE000 0xDFFF 0xDF80 0xDF00 0xDEFF 0xDE40 0xDE3F 0xDE00 0xDDFF
0xFFFF
Hardware SFR registers Hardware radio / I2S registers USB registers ( )
Xdata (and Unified Code) memory space
0x8000 0x7FFF
Non-volatile program memory 32 kB
32 kB Flash
0x0000
0x0000
8051 memory spaces
CC2510/2511 XDATA memory space
Physical memory
Figure 10: CC2510FX/CC2511Fx XDATA memory space (CC2510F32/CC2511F32 shown here)
12.3.2 Memory Space This section describes the details of each CPU memory space. The caption of each chapter refer to the memory spaces in a standard 8051, any differences between the standard 8051 and CC2510FX/CC2511Fx is described. XDATA memory space. On a standard 8051 this memory space would hold any extra RAM available (in addition to the 128/256 byte DATA)
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CC2510FX / CC2511Fx
The CC2510FX/CC2511Fx has a total of 1, 2 or 4 KB SRAM, starting at address 0xF000. Compilers/assemblers must take into consideration that the first address of usable SRAM starts at address 0xF000 instead of 0x0000. The 256 bytes from 0xFF00 to 0xFFFF are the DATA memory mapped to XDATA. These bytes are also reached through the DATA memory space. The 350 bytes of XDATA in location 0xFDA20xFEFF on CC2510F32 and CC2511F32 do DATA RAM CC251xF8 CC251xF16 CC251xF32 0xFF00 - 0xFFFF 0xFF00 - 0xFFFF 0xFF00 - 0xFFFF No Retention RAM - - 0xFDA2 - 0xFEFF XDATA RAM 0xF000 - 0xF2FF 0xF000 - 0xF6FF 0xF000 - 0xFDA9 Flash Memory 0x0000 - 0x1FFF 0x0000 - 0x3FFF 0x0000 - 0x7FFF not retain data when power modes PM2/3 are entered. However these bytes may be used in PM0 and PM1 on the F32 versions. The rest of the SRAM will retain its contents in PM0 to 3. Refer to section 13.10 on page 140 for a detailed description of power modes. See Table 28 for an overview of the SRAM and Flash memory map.
Table 28 SRAM and Flash Memory Map In addition the following is mapped into the XDATA memory space: * The 8, 16 and 32 KB flash program memory (CODE) is mapped into the address ranges 0x0000-0x1FFF, 0x0000-0x3FFF and 0x0000-0x7FFF respectively. Radio registers are mapped address range 0xDF00-0xDF3D. into On a standard 8051 this memory space would hold the program memory, where the MCU reads the program/instructions. The CC2510FX/CC2511Fx has 8, 16 or 32 KB flash program memory intended to hold the MCU program. The Flash is mapped into CODE and starts at address 0x0000. In addition all other memory spaces are mapped into the CODE memory space. The mapping is identical to XDATA (see the XDATA memory space) Thus the CC2510FX/CC2511Fx MCU may execute a program stored in SRAM. This allows the program to be easily updated without writing to flash (which have a limited erase/write cycles) This is particularly useful on the CC2511Fx, where parts of the firmware can be downloaded from the windows USB driver. Executing a program from SRAM instead of FLASH will also result in a lower power consumption and may be interesting for battery powered devices.
* * *
I2S registers are mapped into the address range 0xDF40-0xDF48. All SFR except the registers shown in gray in Table 29. are mapped into address range 0xDF80-0xDFFF. The USB registers are mapped into the address range 0xDE00-0xDE3F on the CC2511Fx, but are not implemented on the CC2510FX.
*
This memory mapping allows the DMA controller (and the CPU) access to all the physical memories in a single unified address space.
DATA memory space. CODE memory space.
CC2510FX/CC2511Fx is identical to a standard
8051, with 256 byte of RAM accessible through the 8-bit address range of DATA
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The
DATA
memory
space
of
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CC2510FX / CC2511Fx
memory. Just like a standard 8051 the upper 128 byte share address with the SFR and can only be accessed indirectly, the stack is normally located here. The lower 48 bytes are reserved, and hold 4 register banks used by the MCU. The 16 bytes on addresses 0x20 to 0x2F are bit addressable. The DATA memory will retain its contents in PM0 to 3 The DATA memory can be accessed through the XDATA and CODE memory spaces at the address ranges 0xFF00-0xFFFF. space and not through the duplicate mapping into XDATA/CODE memory space, these registers are shown in gray in Table 29.
12.3.3 Data Pointers The CC2510FX/CC2511Fx has two data pointers, DPTR0 and DPTR1 to accelerate the movement of data blocks to/from memory. The data pointers are generally used to access CODE or XDATA space e.g.
MOVC A,@A+DPTR MOV A,@DPTR.
SFR memory space. The SFR memory space is identical to a standard 8051. The 128-entry hardware register area is accessed through this memory space. Unlike a standard 8051, the SFR registers are also accessible through the XDATA and CODE address space at the address range 0xDF80-0xDFFF. Some CPU-specific SFR registers reside inside the CPU core and can only be accessed using the SFR memory DPH0 (0x83) - Data Pointer 0 High Byte
Bit Name Reset R/W
The data pointer select bit, bit 0 in the Data Pointer Select register DPS, chooses which data pointer shall be the active one during execution of an instruction that uses the data pointer, e.g. in one of the above instructions. The data pointers are two bytes consisting of the following SFRs: * * DPTR0 - DPH0:DPL0 DPTR1 - DPH1:DPL1 wide
Description Data pointer 0, high byte
7:0
DPH0[7:0]
0
R/W
DPL0 (0x82) - Data Pointer 0 Low Byte
Bit Name Reset R/W Description Data pointer 0, low byte
7:0
DPL0[7:0]
0
R/W
DPH1 (0x85) - Data Pointer 1 High Byte
Bit Name Reset R/W Description Data pointer 1, high byte
7:0
DPH1[7:0]
0
R/W
DPL1 (0x84) - Data Pointer 1 Low Byte
Bit Name Reset R/W Description Data pointer 1, low byte
7:0
DPL1[7:0]
0
R/W
DPS (0x92) - Data Pointer Select
Bit Name Reset R/W Description Not used
7:1
-
0x00
R0
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CC2510FX / CC2511Fx
Bit Name Reset R/W Description Data pointer select. Selects active data pointer. 0 DPTR0 1 DPTR1
0
DPS
0
R/W
12.3.4 XDATA Memory Access The CC2510FX/CC2511Fx provides an additional SFR register MPAGE. This register is used during instructions MOVX A,@Ri and MOVX @Ri,A MPAGE gives the 8 most significant address bits, while the register Ri gives the 8 least significant bits.
In some 8051 implementations, this type of XDATA access is performed using P2 to give the most significant address bits. Existing software may therefore have to be adapted to make use of MPAGE instead of P2.
MPAGE (0x93)- Memory Page Select
Bit Name Reset R/W Description Memory page, high-order bits of address in MOVX instruction
7:0
MPAGE[7:0]
0x00
R/W
12.4 SFR Registers The Special Function Registers (SFRs) control several of the features of the 8051 CPU core and/or peripherals. Many of the 8051 core SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs that control features that are not available in the standard 8051. The additional SFRs are used to interface with the peripheral units and RF transceiver. Table 29 shows the address to all SFRs in CC2510FX/CC2511Fx. The 8051 internal SFRs are shown with grey background, while the the other SFRs are specific to CC2510FX/CC2511Fx .
Note: all internal SFRs (shown with grey background in Table 29), can only be accessed through SFR space as these registers are not mapped into XDATA space. Table 30 lists the additional SFRs that are not standard 8051 peripheral SFRs or CPUinternal SFRs. The additional SFRs are described in the relevant sections for each peripheral function.
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CC2510FX / CC2511Fx
8 bytes 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8 E0 E8 F0 F8 P0 TCON P1 S0CON P2 IEN0 IEN1 IRCON PSW TIMIF ACC IRCON2 B U1CSR SP P0IFG RFIM WORIRQ IP0 ENCDI IP1 U0DBUF WDCTL DMAIRQ RFD RFST RFIF PERCFG U1DBUF DPL0 P1IFG DPS IEN2 WORCTL ENCDO ADCL U0BAUD T3CNT DMA1CFGL T1CC0L T1CNTL T4CNT ADCCFG U1BAUD DPH0 P2IFG MPAGE S1CON WOREVT0 FWT ENCCS ADCH T3CTL DMA1CFGH T1CC0H T1CNTH T4CTL P0SEL U1UCR DPL1 PICTL T2CT WOREVT1 FADDRL ADCCON1 RNDL U0UCR T3CCTL0 DMA0CFGL T1CC1L T1CTL T4CCTL0 P1SEL U1GCR DPH1 P1IEN ENDIAN T2PR WORTIME0 FADDRH ADCCON2 RNDH U0GCR T3CC0 DMA0CFGH T1CC1H T1CCTL0 T4CC0 P2SEL P0DIR U0CSR T2CTL WORTIME1 FCTL ADCCON3 SLEEP CLKCON T3CCTL1 DMAARM T1CC2L T1CCTL1 T4CCTL1 P1INP P1DIR PCON P0INP FWDATA MEMCTR T3CC1 DMAREQ T1CC2H T1CCTL2 T4CC1 P2INP P2DIR 87 8F 97 9F A7 AF B7 BF C7 CF D7 DF E7 EF F7 FF
Table 29: SFR address overview
Table 30: CC2510FX/CC2511Fx specific SFR overview
Register name ADCCON1 ADCCON2 ADCCON3 ADCL ADCH RNDL RNDH ENCDI ENCDO ENCCS DMAIRQ DMA1CFGL DMA1CFGH DMA0CFGL DMA0CFGH DMAARM DMAREQ FWT FADDRL FADDRH SFR Address 0xB4 0xB5 0xB6 0xBA 0xBB 0xBC 0xBD 0xB1 0xB2 0xB3 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xAB 0xAC 0xAD Module ADC ADC ADC ADC ADC ADC ADC AES AES AES DMA DMA DMA DMA DMA DMA DMA FLASH FLASH FLASH Description ADC Control 1 ADC Control 2 ADC Control 3 ADC Data Low ADC Data High Random Number Generator Data Low Random Number Generator Data High Encryption/Decryption Input Data Encryption/Decryption Output Data Encryption/Decryption Control and Status DMA Interrupt Flag DMA Channel 1-4 Configuration Address Low DMA Channel 1-4 Configuration Address High DMA Channel 0 Configuration Address Low DMA Channel 0 Configuration Address High DMA Channel Arm DMA Channel Start Request and Status Flash Write Timing Flash Address Low Flash Address High
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CC2510FX / CC2511Fx
Register name FCTL FWDATA P0IFG P1IFG P2IFG PICTL P1IEN P0INP PERCFG ADCCFG P0SEL P1SEL P2SEL P1INP P2INP P0DIR P1DIR P2DIR MEMCTR SLEEP CLKCON RFIM RFD RFIF RFST WORIRQ WORCTRL WOREVT0 WOREVT1 WORTIME0 WORTIME1 T1CC0L T1CC0H T1CC1L T1CC1H T1CC2L T1CC2H T1CNTL T1CNTH T1CTL T1CCTL0 SFR Address 0xAE 0xAF 0x89 0x8A 0x8B 0x8C 0x8D 0x8F 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xFD 0xFE 0xFF 0xC7 0xBE 0xC6 0x91 0xD9 0xE9 0xE1 0xA1 0xA2 0xA3 0xA5 0xA4 0xA6 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE2 0xE3 0xE4 0xE5 Module FLASH FLASH IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC IOC MEMORY PMC PMC RF RF RF RF Sleep Timer Sleep Timer Sleep Timer Sleep Timer Sleep Timer Sleep Timer Timer1 Timer1 Timer1 Timer1 Timer1 Timer1 Timer1 Timer1 Timer1 Timer1 Description Flash Control Flash Write Data Port 0 Interrupt Status Flag Port 1 Interrupt Status Flag Port 2 Interrupt Status Flag Port Pins Interrupt Mask and Edge Port 1 Interrupt Mask Port 0 Input Mode Peripheral I/O Control ADC Input Configuration Port 0 Function Select Port 1 Function Select Port 2 Function Select Port 1 Input Mode Port 2 Input Mode Port 0 Direction Port 1 Direction Port 2 Direction Memory System Control Sleep Mode Control Clock Control RF Interrupt Mask RF Data RF Interrupt flags RF Strobe Commands Sleep Timer Interrupts Sleep Timer Control Sleep Timer Event 0 Timeout Low Byte Sleep Timer Event 0 Timeout High Byte Sleep Timer Low Byte Sleep Timer High Byte Timer 1 Channel 0 Capture/Compare Value Low Timer 1 Channel 0 Capture/Compare Value High Timer 1 Channel 1 Capture/Compare Value Low Timer 1 Channel 1 Capture/Compare Value High Timer 1 Channel 2 Capture/Compare Value Low Timer 1 Channel 2 Capture/Compare Value High Timer 1 Counter Low Timer 1 Counter High Timer 1 Control and Status Timer 1 Channel 0 Capture/Compare Control
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CC2510FX / CC2511Fx
Register name T1CCTL1 T1CCTL2 T2CT T2PR T2CTL T3CNT T3CTL T3CCTL0 T3CC0 T3CCTL1 T3CC1 T4CNT T4CTL T4CCTL0 T4CC0 T4CCTL1 T4CC1 TIMIF U0CSR U0DBUF U0BAUD U0UCR U0GCR U1CSR U1DBUF U1BAUD U1UCR U1GCR ENDIAN WDCTL SFR Address 0xE6 0xE7 0x9C 0x9D 0x9E 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xD8 0x86 0xC1 0xC2 0xC4 0xC5 0xF8 0xF9 0xFA 0xFB 0xFC 0x95 0xC9 Module Timer1 Timer1 Timer2 Timer2 Timer2 Timer3 Timer3 Timer3 Timer3 Timer3 Timer3 Timer4 Timer4 Timer4 Timer4 Timer4 Timer4 TMINT USART0 USART0 USART0 USART0 USART0 USART1 USART1 USART1 USART1 USART1 MEMORY WDT Description Timer 1 Channel 1 Capture/Compare Control Timer 1 Channel 2 Capture/Compare Control Timer 2 Timer Count Timer 2 Prescaler Timer 2 Control Timer 3 Counter Timer 3 Control Timer 3 Channel 0 Capture/Compare Control Timer 3 Channel 0 Capture/Compare Value Timer 3 Channel 1 Capture/Compare Control Timer 3 Channel 1 Capture/Compare Value Timer 4 Counter Timer 4 Control Timer 4 Channel 0 Capture/Compare Control Timer 4 Channel 0 Capture/Compare Value Timer 4 Channel 1 Capture/Compare Control Timer 4 Channel 1 Capture/Compare Value Timers 1/3/4 Joint Interrupt Mask/Flags USART 0 Control and Status USART 0 Receive/Transmit Data Buffer USART 0 Baud Rate Control USART 0 UART Control USART 0 Generic Control USART 1 Control and Status USART 1 Receive/Transmit Data Buffer USART 1 Baud Rate Control USART 1 UART Control USART 1 Generic Control USB Endianess Control (CC2511Fx) Watchdog Timer Control
12.5 CPU Registers This section describes the internal registers used by the CPU. 12.5.1 Registers R0-R7 The CC2510FX/CC2511Fx provides four register banks of eight registers each. These register banks are mapped in the DATA memory space 12.5.2 Program Status Word at addresses 0x00-0x07, 0x08-0x0F, 0x100x17 and 0x18-0x1F. Each register bank contains the eight 8-bit register R0-R7. The register bank to be used is selected through the Program Status Word PSW.RS[1:0].
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The Program Status Word (PSW) contains several bits that show the current state of the CPU. The Program Status Word is accessible as an SFR and it is bit-addressable. PSW contains the Carry flag, Auxiliary Carry flag for BCD operations, Register Select bits, Overflow flag and Parity flag. Two bits in PSW are uncommitted and can be used as user-defined status flags .
PSW (0xD0) - Program Status Word
Bit 7 Name Reset 0 R/W R/W Description Carry flag. Set to 1 when the last arithmetic operation resulted in a carry (during addition) or borrow (during subtraction), otherwise cleared to 0 by all arithmetic operations. Auxiliary carry flag for BCD operations. Set to 1 when the last arithmetic operation resulted in a carry into (during addition) or borrow from (during subtraction) the high order nibble, otherwise cleared to 0 by all arithmetic operations. User-defined, bit-addressable Register bank select bits. Selects which set of R7-R0 registers to use from four possible register banks in DATA space. 00 01 10 11 2 Bank 0, 0x00 - 0x07 Bank 1, 0x08 - 0x0F Bank 2, 0x10 - 0x17 Bank 3, 0x18 - 0x1F
CY
6
AC
0
R/W
5 4:3
F0 RS[1:0]
0 00
R/W R/W
OV
0
R/W
Overflow flag, set by arithmetic operations. Set to 1 when the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). Otherwise, the bit is cleared to 0 by all arithmetic operations. User-defined, bit-addressable Parity flag, parity of accumulator set by hardware to 1 if it contains an odd number of 1's, otherwise it is cleared to 0
1 0
F1 P
0 0
R/W R/W
12.5.3 Accumulator ACC is the accumulator. This is the source and destination of most arithmetic instructions, data transfer and other instructions. The ACC (0xE0) - Accumulator
Bit Name Reset R/W Description Accumulator
mnemonic for the accumulator (in instructions involving the accumulator) refers to A instead of ACC.
7:0
ACC[7:0]
0x00
R/W
12.5.4 B Register The B register is used as the second 8-bit argument during execution of multiply and divide instructions. When not used for these purposes it may be used as a scratch-pad register to hold temporary data.
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B (0xF0) - B Register
Bit Name Reset R/W Description B register. Used in MUL/DIV instructions.
7:0
B[7:0]
0x00
R/W
12.5.5 Stack Pointer The stack resides in DATA memory space and grows upwards. The PUSH instruction first increments the Stack Pointer (SP) and then copies the byte into the stack. The Stack Pointer is initialized to 0x07 after a reset and it is incremented once to start from location SP (0x81) - Stack Pointer
Bit Name Reset R/W Description Stack Pointer
0x08, which is the first register (R0) of the second register bank. Thus, in order to use more than one register bank, the SP should be initialized to a different location not used for data storage.
7:0
SP[7:0]
0x07
R/W
12.6 Instruction Set Summary The 8051 instruction set is summarized in
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CC2510FX / CC2511Fx
Table 31. All mnemonics copyrighted (c) Intel Corporation 1980. The following conventions are used in the instruction set summary: * * Rn - Register R7-R0 of the currently selected register bank. direct - 8-bit internal data location's address. This can be DATA area (0x00 - 0x7F) or SFR area (0x80 - 0xFF). @Ri - 8-bit internal data location, DATA area (0x00 - 0xFF) addressed indirectly through register R1 or R0. #data - 8-bit instruction. constant included in * * anywhere within the 8/16/32 KB CODE program memory space. addr11 - 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 KB page of program memory as the first byte of the following instruction. rel - Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. bit - direct addressed bit in DATA area or SFR.
*
*
* * *
#data16 - 16-bit constant included in instruction. addr16 - 16-bit destination address. Used by LCALL and LJMP. A valid branch can be
The instructions that affect CPU flag settings located in PSW are listed in Table 32 on page 49. Note that operations on the PSW or bits in PSW will also affect the flag settings.
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CC2510FX / CC2511Fx
Table 31. Instruction Set Summary
Mnemonic Description Arithmetic operations ADD A,Rn ADD A,direct ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,direct ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,direct SUBB A,@Ri SUBB A,#data INC A INC Rn INC direct INC @Ri INC DPTR DEC A DEC Rn DEC direct DEC @Ri MUL AB DIV DA A Add register to accumulator Add direct byte to accumulator Add indirect RAM to accumulator Add immediate data to accumulator Add register to accumulator with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment accumulator Increment register Increment direct byte Increment indirect RAM Increment data pointer Decrement accumulator Decrement register Decrement direct byte Decrement indirect RAM Multiply A and B Divide A by B Decimal adjust accumulator Logical operations ANL A,Rn ANL A,direct ANL A,@Ri ANL A,#data ANL direct,A ANL direct,#data ORL A,Rn ORL A,direct ORL A,@Ri ORL A,#data ORL direct,A ORL direct,#data XRL A,Rn AND register to accumulator AND direct byte to accumulator AND indirect RAM to accumulator AND immediate data to accumulator AND accumulator to direct byte AND immediate data to direct byte OR register to accumulator OR direct byte to accumulator OR indirect RAM to accumulator OR immediate data to accumulator OR accumulator to direct byte OR immediate data to direct byte Exclusive OR register to accumulator 58-5F 55 56-57 54 52 53 48-4F 45 46-47 44 42 43 68-6F 1 2 1 2 2 3 1 2 1 2 2 3 1 1 2 2 2 3 4 1 2 2 2 3 4 1 28-2F 25 26-27 24 38-3F 35 36-37 34 98-9F 95 96-97 94 04 08-0F 05 06-07 A3 14 18-1F 15 16-17 A4 84 D4 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 1 2 1 1 1 1 1 2 2 2 1 2 2 2 1 2 2 2 1 2 3 3 1 1 2 3 3 5 5 1 Hex Opcode Bytes Cycles
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Mnemonic XRL A,direct XRL A,@Ri XRL A,#data XRL direct,A XRL direct,#data CLR A CPL A RL A RLC A RR A RRC A SWAP A Description Exclusive OR direct byte to accumulator Exclusive OR indirect RAM to accumulator Exclusive OR immediate data to accumulator Exclusive OR accumulator to direct byte Exclusive OR immediate data to direct byte Clear accumulator Complement accumulator Rotate accumulator left Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right through carry Swap nibbles within the accumulator Data transfers MOV A,Rn MOV A,direct MOV A,@Ri MOV A,#data MOV Rn,A MOV Rn,direct MOV Rn,#data MOV direct,A MOV direct,Rn MOV direct1,direct2 MOV direct,@Ri MOV direct,#data MOV @Ri,A MOV @Ri,direct MOV @Ri,#data MOV DPTR,#data16 MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH direct POP direct XCH A,Rn XCH A,direct XCH A,@Ri XCHD A,@Ri Move register to accumulator Move direct byte to accumulator Move indirect RAM to accumulator Move immediate data to accumulator Move accumulator to register Move direct byte to register Move immediate data to register Move accumulator to direct byte Move register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate data to direct byte Move accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Load data pointer with a 16-bit constant Move code byte relative to DPTR to accumulator Move code byte relative to PC to accumulator Move external RAM (8-bit address) to A Move external RAM (16-bit address) to A Move A to external RAM (8-bit address) Move A to external RAM (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange register with accumulator Exchange direct byte with accumulator Exchange indirect RAM with accumulator Exchange low-order nibble indirect. RAM with A E8-EF E5 E6-E7 74 F8-FF A8-AF 78-7F F5 88-8F 85 86-87 75 F6-F7 A6-A7 76-77 90 93 83 E2-E3 E0 F2-F3 F0 C0 D0 C8-CF C5 C6-C7 D6-D7 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 2 2 2 4 2 3 3 4 4 3 3 5 3 3 3 3 3-10 3-10 4-11 4-11 4 3 2 3 3 3 Hex Opcode 65 66-67 64 62 63 E4 F4 23 33 03 13 C4 Bytes 2 1 2 2 3 1 1 1 1 1 1 1 Cycles 2 2 2 3 4 1 1 1 1 1 1 1
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Mnemonic Description Program branching ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel JC rel JNC JB bit,rel JNB bit,rel JBC bit,direct rel CJNE A,direct rel CJNE A,#data rel CJNE Rn,#data rel CJNE @Ri,#data rel DJNZ Rn,rel DJNZ direct,rel NOP Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to the DPTR Jump if accumulator is zero Jump if accumulator is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to reg. and jump if not equal Compare immediate to indirect and jump if not equal Decrement register and jump if not zero Decrement direct byte and jump if not zero No operation Boolean variable operations CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry OR direct bit to carry flag OR complement of direct bit to carry Move direct bit to carry flag Move carry flag to direct bit C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 1 2 1 2 1 2 2 2 2 2 2 2 1 3 1 3 1 3 2 2 2 2 2 3 xxx11 12 22 32 xxx01 02 80 73 60 70 40 50 20 30 10 B5 B4 B8-BF B6-B7 D8-DF D5 00 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 6 6 4 4 3 4 3 2 3 3 3 3 4 4 4 4 4 4 4 3 4 1 Hex Opcode Bytes Cycles
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Instruction ADD ADDC SUBB MUL DIV DA RRC RLC SETB C CLR C CPL C ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit CJNE CY x x x 0 0 x x x 1 x x x x x x x x OV x x x x x AC x x x
"0"=set to 0, "1"=set to 1, "x"=set to 0/1, "-"=not affected Table 32: Instructions that affect flag settings 12.7 Interrupts The CPU has 18 interrupt sources. Each source has its own request flag located in a set of Interrupt Flag SFR registers. Each interrupt requested by the corresponding flag can be individually enabled or disabled. The definitions of the interrupt sources and the interrupt vectors are given in Table 33. I2S and USART1 share interrupts. On the CC2511Fx USB shares interrupt with Port 2 inputs. The interrupt aliases for I2S and USB are listed in Table 34. The original interrupt names, masks and flags in Table 33, however, are used in the following sections. The interrupts are grouped into a set of priority level groups with selectable priority levels. The interrupt enable registers are described in section 12.7.1 and the interrupt priority settings are described in section 12.7.4 on page 58. 12.7.1 Interrupt Masking Each interrupt can be individually enabled or disabled by the interrupt enable bits in the Interrupt Enable SFRs IEN0, IEN1 and IEN2. The Interrupt Enable SFRs are described below and summarized in Table 33. Note that some peripherals have several events that can generate the interrupt request associated with that peripheral. This applies to Port 0, Port 1, Port 2, DMA, Timer 1, Timer 3 , Timer 4 and Radio. These peripherals have interrupt mask bits for each internal interrupt source in the corresponding SFR registers. In order to use any of the interrupts in the CC2510FX/CC2511Fx the following steps must be taken 1. Set the corresponding individual interrupt enable bit in the IEN0, IEN1 or IEN2 register to 1. 2. Set individual interrupt enable bit in the peripherals SFR register, if any. 3. Begin the interrupt service routine at the corresponding vector address of that interrupt. See Table 33 for addresses. 4. Enable global interrupt by setting the EA bit in IEN0 to 1
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12.7.2 Interrupt Vector Sharing I2S shares RX and TX interrupt vectors with USART1 and the USB Controller (on CC2511Fx) shares interrupt vector with Port 2 inputs. See Table 34 for addresses.
Interrupt number 0 1 2 3
Description RF TX done / RX ready ADC end of conversion USART0 RX complete USART1 RX complete (I2S RX complete, see Table 34)
Interrupt name RFTXRX ADC URX0 URX1
Interrupt Vector 03h 0Bh 13h 1Bh
Interrupt Mask IEN0.RFTXRXIE IEN0.ADCIE IEN0.URX0IE IEN0.URX1IE
Interrupt Flag TCON.RFTXRXIF TCON.ADCIF TCON.URX0IF TCON.URX1IF
4 5 6
AES encryption/decryption complete Sleep Timer compare Port 2 inputs (Also used for USB on CC2511Fx,, see Table 34)
ENC ST P2INT
23h 2Bh 33h
IEN0.ENCIE IEN0.STIE IEN2.P2IE
S0CON.ENCIF IRCON.STIF IRCON2.P2IF
7 8 9 10 11 12 13
USART0 TX complete DMA transfer complete Timer 1 (16-bit) capture/Compare/overflow Timer 2 (MAC Timer) overflow Timer 3 (8-bit) capture/compare/overflow Timer 4 (8-bit) capture/compare/overflow Port 0 inputs (Note: USB Resume from suspend interrupt on P0_7 on CC2511Fx )
UTX0 DMA T1 T2 T3 T4 P0INT
3Bh 43h 4Bh 53h 5Bh 63h 6Bh
IEN2.UTX0IE IEN1.DMAIE IEN1.T1IE IEN1.T2IE IEN1.T3IE IEN1.T4IE IEN1.P0IE
IRCON2.UTX0IF IRCON.DMAIF IRCON.T1IF IRCON.T2IF IRCON.T3IF IRCON.T4IF IRCON.P0IF
14
USART1 TX complete (I2S TX complete, see Table 34)
UTX1
73h
IEN2.UTX1IE
IRCON2.UTX1IF
15 16 17
Port 1 inputs RF general interrupts Watchdog overflow in timer mode
P1INT RF WDT
7Bh 83h 8Bh
IEN2.P1IE IEN2.RFIE IEN2.WDTIE
IRCON2.P1IF S1CON.RFIF IRCON2.WDTIF
Table 33: Interrupts Overview
Interrupt number 3 14 6
Description I2S RX complete I2S TX complete USB Interrupt pending (CC2511Fx )
Interrupt name I2SRX I2STX USB
Interrupt Vector 1Bh 73h 33h
Interrupt Mask Alias IEN0.I2SRXIE IEN2.I2STXIE IEN2.USBIE
Interrupt Flag Alias TCON.I2SRXIF IRCON2.I2STXIF IRCON2.USBIF
Table 34: Shared Interrupt Vectors (I2S and USB)
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IEN0 (0xA8) - Interrupt Enable 0 Register
Bit 7 Name Reset 0 R/W R/W Description Disables all interrupts. 0 1 6 5 No interrupt will be acknowledged Each interrupt source is individually enabled or disabled by setting its corresponding enable bit
EA
STIE
0 0
R0 R/W
Not used. Read as 0 STIE - Sleep Timer interrupt enable 0 1 Interrupt disabled Interrupt enabled
4
ENCIE
0
R/W
ENCIE - AES encryption/decryption interrupt enable 0 1 Interrupt disabled Interrupt enabled
3
URX1IE / I2SRXIE
0
R/W
URX1IE- USART1 RX interrupt enable / I2SRXIE - I2S RX interrupt enable 0 1 Interrupt disabled Interrupt enabled
2
URX0IE
0
R/W
URX0IE - USART0 RX interrupt enable 0 1 Interrupt disabled Interrupt enabled
1
ADCIE
0
R/W
ADCIE - ADC interrupt enable 0 1 Interrupt disabled Interrupt enabled
0
RFTXRXIE
0
R/W
RFRXTXIE - RF TX/RX done interrupt enable 0 1 Interrupt disabled Interrupt enabled
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IEN1 (0xB8) - Interrupt Enable 1 Register
Bit 7:6 5 Name Reset 00 0 R/W R0 R/W Description Not used. Read as 0 P0IE - Port 0 interrupt enable 0 1 4 Interrupt disabled Interrupt enabled
P0IE
T4IE
0
R/W
T4IE - Timer 4 interrupt enable 0 1 Interrupt disabled Interrupt enabled
3
T3IE
0
R/W
T3IE - Timer 3 interrupt enable 0 1 Interrupt disabled Interrupt enabled
2
T2IE
0
R/W
T2IE - Timer 2 interrupt enable 0 1 Interrupt disabled Interrupt enabled
1
T1IE
0
R/W
T1IE - Timer 1 interrupt enable 0 1 Interrupt disabled Interrupt enabled
0
DMAIE
0
R/W
DMAIE - DMA transfer interrupt enable 0 1 Interrupt disabled Interrupt enabled
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IEN2 (0x9A) - Interrupt Enable 2 Register
Bit 7:6 5 Name Reset 00 0 R/W R0 R/W Description Not used. Read as 0 WDTIE - Watchdog timer interrupt enable 0 1 4 Interrupt disabled Interrupt enabled
WDTIE
P1IE
0
R/W
P1IE - Port 1 interrupt enable 0 1 Interrupt disabled Interrupt enabled
3
UTX1IE / I2STXIE
0
R/W
UTX1IE - USART1 TX interrupt enable / I2STXIE - I2S TX interrupt enable 0 1 Interrupt disabled Interrupt enabled
2
UTX0IE
0
R/W
UTX0IE - USART0 TX interrupt enable 0 1 Interrupt disabled Interrupt enabled
1
P2IE / USBIE
0
R/W
P2IE - Port 2 interrupt enable (Also used for USB interrupt enable on CC2511Fx) 0 1 Interrupt disabled Interrupt enabled
0
RFIE
0
R/W
RFIE - RF general interrupt enable 0 1 Interrupt disabled Interrupt enabled
12.7.3 Interrupt Processing When an interrupt occurs, the CPU will vector to the interrupt vector address as shown in Table 33. Once an interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a RETI return from interrupt instruction. When a RETI is performed, the CPU will return to the instruction that would have been next when the interrupt occurred. When the interrupt condition occurs, the CPU will also indicate this by setting an interrupt flag bit in the interrupt flag registers. This bit is set regardless of whether the interrupt is enabled or disabled. If the interrupt is enabled when an interrupt flag is set, then on the next instruction cycle the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address. Interrupt response will require a varying amount of time depending on the state of the CPU when the interrupt occurs. If the CPU is performing an interrupt service with equal or greater priority, the new interrupt will be pending until it becomes the interrupt with highest priority. In other cases, the response time depends on current instruction. The fastest possible response to an interrupt is seven instruction cycles. This includes one instruction cycle for detecting the interrupt and six cycles to perform the LCALL. Clearing interrupt flags must be done correctly to ensure that no interrupts are lost, and no interrupt is processed more than once. The general rule is to first clear the MCU interrupt flag, and then clear any module flags. E.g. on the RF interrupt the MCU interrupt flag located in S1CON.RFIF is cleared first and
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then the module interrupt flags located in the RFIF register are cleared. One or more module flags can be cleared at once. However the safest approach is to only handle one interrupt source each time the interrupt is triggered, hence clearing only one module flag. When any module flag is cleared the chip will check if there are any module interrupt flags left that are both enabled and set, if so the MCU interrupt flag will be set and a new interrupt triggered. Example code where only one module flag is handled and cleared each time the interrupt occurs:
#pragma vector=RF_VECTOR __interrupt void rf_interrupt (void) { S1CON &= ~0x03; //clear MCU interrupt flag if(RFIF & 0x80) //if TX underflow { ....handle TX underflow RFIF = ~0x80; //clear module interrupt flag } else if(RFIF & 0x40) //else if RX overflow { ....handle RX overflow RFIF = ~0x40; //clear module interrupt flag } .....use "else if" to check and handle other RFIF flags }
Some interrupts are cleared by hardware when the CPU vectors the interrupt service routine, when handling these interrupts the MCU interrupt flag should NOT be cleared in software, only clear module interrupt flags. This applies to the following interrupts: * * * * * * * * RFTXRX ADC URX0 URX1/I2SRX T1 T2 T3 T4
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TCON (0x88) - Interrupt Flag
Bit 7 Name Reset 0 R/W R/W H0 Description URX1IF - USART1 RX interrupt flag. / I2SRXIF - I2S RX interrupt flag. Set to 1 when USART1 RX interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 1 6 5 Interrupt not pending Interrupt pending
URX1IF / I2SRXIF
ADCIF
0 0
R/W R/W H0
Not used ADCIF - ADC interrupt flag. Set to 1 when ADC interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 1 Interrupt not pending Interrupt pending
4 3
URX0IF
0 0
R/W R/W H0
Not used URX0IF - USART0 RX interrupt flag. Set to 1 when USART0 interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 1 Interrupt not pending Interrupt pending
2 1
IT1 RFTXRXIF
1 0
R/W R/W H0
Reserved. Must always be set to 1. RFTXRXIF - RF TX/RX complete interrupt flag. Set to 1 when RFTXRX interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 1 Interrupt not pending Interrupt pending
0
IT0
1
R/W
Reserved. Must always be set to 1.
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S0CON (0x98) - Interrupt Flag 2
Bit 7:6 1 Name Reset 0 0 R/W R/W R/W Description Not used ENCIF - AES interrupt. ENCIF has two interrupt flags, ENCIF_1 and ENCIF_0. Setting one of these flags will request interrupt service. Both flags are set when the AES co-processor requests the interrupt. 0 1 0 Interrupt not pending Interrupt pending
ENCIF_1
ENCIF_0
0
R/W
ENCIF - AES interrupt. ENCIF has two interrupt flags, ENCIF_1 and ENCIF_0. Setting one of these flags will request interrupt service. Both flags are set when the AES co-processor requests the interrupt. 0 1 Interrupt not pending Interrupt pending
S1CON (0x9B) - Interrupt Flag 3
Bit 7:6 1 Name Reset 0 0 R/W R/W R/W Description Not used RFIF - RF general interrupt. RFIF has two interrupt flags, RFIF_1 and RFIF_0. Setting one of these flags will request interrupt service. Both flags are set when the radio requests the interrupt. 0 1 0 Interrupt not pending Interrupt pending
RFIF_1
RFIF_0
0
R/W
RFIF - RF general interrupt. RFIF has two interrupt flags, RFIF_1 and RFIF_0. Setting one of these flags will request interrupt service. Both flags are set when the radio requests the interrupt. 0 1 Interrupt not pending Interrupt pending
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IRCON (0xC0) - Interrupt Flag 4
Bit 7 Name Reset 0 R/W R/W Description STIF - Sleep timer interrupt flag 0 1 6 5 Interrupt not pending Interrupt pending
STIF
P0IF
0 0
R/W R/W
Not used P0IF - Port 0 interrupt flag 0 1 Interrupt not pending Interrupt pending
4
T4IF
0
R/W H0
T4IF - Timer 4 interrupt flag. Set to 1 when Timer 4 interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 1 Interrupt not pending Interrupt pending
3
T3IF
0
R/W H0
T3IF - Timer 3 interrupt flag. Set to 1 when Timer 3 interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 1 Interrupt not pending Interrupt pending
2
T2IF
0
R/W H0
T2IF - Timer 2 interrupt flag. Set to 1 when Timer 2 interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 1 Interrupt not pending Interrupt pending
1
T1IF
0
R/W H0
T1IF - Timer 1 interrupt flag. Set to 1 when Timer 1 interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 1 Interrupt not pending Interrupt pending
0
DMAIF
0
R/W
DMAIF - DMA complete interrupt flag. 0 1 Interrupt not pending Interrupt pending
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IRCON2 (0xE8) - Interrupt Flag 5
Bit 7:5 4 Name Reset 00 0 R/W R/W R/W Description Not used WDTIF - Watchdog timer interrupt flag. 0 1 3 Interrupt not pending Interrupt pending
WDTIF
P1IF
0
R/W
P1IF - Port 1 interrupt flag. 0 1 Interrupt not pending Interrupt pending
2
UTX1IF / I2STXIF
0
R/W
UTX1IF - USART1 TX interrupt flag. / I2STXIF - I2S TX interrupt flag 0 1 Interrupt not pending Interrupt pending
1
UTX0IF
0
R/W
UTX0IF - USART0 TX interrupt flag. 0 1 Interrupt not pending Interrupt pending
0
P2IF / USBIF
0
R/W
P2IF - Port2 interrupt flag. / USBIF - USB interrupt flag 0 1 Interrupt not pending Interrupt pending
12.7.4 Interrupt Priority The interrupts are grouped into six interrupt priority groups and the priority for each group is set by the registers IP0 and IP1. In order to assign a higher priority to an interrupt, i.e. to its interrupt group, the corresponding bits in IP0 and IP1 must be set as shown in Table 35 on page 59. The interrupt priority groups with assigned interrupt sources are shown in Table 36. Each group is assigned one of four priority levels. While an interrupt service request is in progress, it cannot be interrupted by a lower or same level interrupt. In the case when same priority simultaneously, the Table 37 is used to request. interrupt requests of the level are received polling sequence shown in resolve the priority of each
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IP1 (0xB9) - Interrupt Priority 1
Bit 7:6 5 4 3 2 1 0 Name Reset 00 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Not used. Interrupt group 5, priority control bit 1, refer to Table 35 Interrupt group 4, priority control bit 1, refer to Table 35 Interrupt group 3, priority control bit 1, refer to Table 35 Interrupt group 2, priority control bit 1, refer to Table 35 Interrupt group 1, priority control bit 1, refer to Table 35 Interrupt group 0, priority control bit 1, refer to Table 35
IP1_5 IP1_4 IP1_3 IP1_2 IP1_1 IP1_0
IP0 (0xA9) - Interrupt Priority 0
Bit 7:6 5 4 3 2 1 0 Name Reset 00 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Not used. Interrupt group 5, priority control bit 0, refer to Table 35 Interrupt group 4, priority control bit 0, refer to Table 35 Interrupt group 3, priority control bit 0, refer to Table 35 Interrupt group 2, priority control bit 0, refer to Table 35 Interrupt group 1, priority control bit 0, refer to Table 35 Interrupt group 0, priority control bit 0, refer to Table 35
IP0_5 IP0_4 IP0_3 IP0_2 IP0_1 IP0_0
IP1_x
IP0_x
Priority Level 0 - lowest 1 2 3 - highest
0 0 1 1
0 1 0 1
Table 35: Priority Level Setting
Group IP0 IP1 IP2 IP3 IP4 IP5
Interrupts RFTXRX ADC URX0 URX1 / I2S ENC ST RF P2INT / USB UTX0 UTX1 / I2S P1INT WDT DMA T1 T2 T3 T4 P0INT
Table 36: Interrupt Priority Groups
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Interrupt number 0 16 8 1 9 2 10 3 11 4 12 5 13 6 7 14 15 17 Interrupt name RFTXRX RF DMA ADC T1 URX0 T2 URX1 / I2S T3 ENC T4 ST P0INT / (USB Resume) P2INT / USB UTX0 UTX1 / I2S P1INT WDT
Polling sequence
Table 37: Interrupt Polling Sequence
12.8 Oscillators and clocks The CC2510FX/CC2511Fx has one internal system clock. The source for the system clock can be either a 13 MHz high speed RC oscillator or a crystal oscillator. The crystal oscillator for CC2510FX operates at 26 MHz while the crystal oscillator for CC2511Fx operates at 48 MHz. The 26 MHz clock is used directly as the system clock for CC2510FX. The 48 MHz clock is used by the USB Controller only while a derived 24 MHz clock is used as the system clock. Clock control is performed using the CLKCON SFR register described in section 13.10. The choice of oscillator allows a trade-off between high-accuracy in the case of the crystal oscillator and low power consumption when the high-frequency RC oscillator is used. Note that operation of the RF transceiver and the USB requires that the crystal oscillator is used.
12.9 Debug Interface The CC2510FX/CC2511Fx includes a debug interface that provides a two-wire interface to an on-chip debug module. The debug interface allows programming the on-chip flash as well providing access to memory and register contents and debug features such as breakpoints, single-stepping and register modification. The debug interface uses the I/O pins P2_1 as Debug Data and P2_2 as Debug Clock during Debug mode. These I/O pins can be used as general purpose I/O only while the device is not in Debug mode. Thus, the debug interface does not interfere with any peripheral I/O pins. Debug mode is not supported in power modes 2 and 3 (PM2, PM3).
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12.9.1 Debug Mode Debug mode is entered by forcing two rising edge transitions on pin P2_2 (Debug Clock) while the RESET_N input is held low. While in Debug mode, pin P2_1 is the Debug Data bi-directional pin and P2_2 is the Debug Clock input pin. 12.9.2 Debug Communication The debug interface uses an SPI-like two-wire interface consisting of the Debug Data (P2_1) and Debug Clock (P2_2) pins. Data is driven on the bi-directional Debug Data pin at the positive edge of Debug Clock and data is sampled on the negative edge of this clock. Debug commands are sent by an external host and consist of 1 to 4 output bytes (including command byte) from the host and an optional input byte read by the host. Figure 11 shows a timing diagram of data on the debug interface. The first byte of the debug command is a command byte and is encoded as follows: * * * bits 7 to 3 : instruction code
bit 2 : return input byte to host when high bits 1 to 0 : number of output bytes from host following instruction code byte
P2_2 P2_1 command first data byte second data byte host input byte
Figure 11: Debug interface timing diagram configuration data byte. The format and description of this configuration data is shown in Table 39. 12.9.6 Debug Status A Debug status byte is read using the READ_STATUS command. The format and description of this debug status is shown in Table 40. The READ_STATUS command is used e.g. for polling the status of flash chip erase after a CHIP_ERASE command or oscillator stable status required for debug commands HALT, RESUME, DEBUG_INSTR, STEP_REPLACE and STEP_INSTR.
12.9.3 Debug Commands The debug commands are shown in Table 38. Some of the debug commands are described in further detail in the following sections 12.9.4 Debug Lock Bit For software code security, the Debug Interface may be locked. When the Debug Lock bit , DBGLOCK, is set (see section 13.16.3) all debug commands except CHIP_ERASE, READ_STATUS and GET_CHIP_ID are disabled and will not function. The CHIP_ERASE command is used to clear the Debug Lock bit. 12.9.5 Debug Configuration The commands WR_CONFIG and RD_CONFIG are used to access the debug
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Command CHIP_ERASE Instruction code 0001 0x00 Description Perform flash chip erase (mass erase) and clear lock bits. If any other command, except READ_STATUS, is issued, then the use of CHIP_ERASE is disabled. Write configuration data. Refer to Table 39 Read configuration data. Returns value set by WR_CONFIG command. Return value of 16-bit program counter. Returns 2 bytes regardless of value of bit 2 in instruction code Read status byte. Refer to Table 40 Set hardware breakpoint Halt CPU operation Resume CPU operation. The CPU must be in halted state for this command to be run. Run debug instruction. The supplied instruction will be executed by the CPU without incrementing the program counter. The CPU must be in halted state for this command to be run. Step CPU instruction. The CPU will execute the next instruction from program memory and increment the program counter after execution. The CPU must be in halted state for this command to be run. Step and replace CPU instruction. The supplied instruction will be executed by the CPU instead of the next instruction in program memory. The program counter will be incremented after execution. The CPU must be in halted state for this command to be run. Return value of 16-bit chip ID and version number. Returns 2 bytes regardless of value of bit 2 of instruction code
WR_CONFIG RD_CONFIG GET_PC READ_STATUS SET_HW_BRKPNT HALT RESUME DEBUG_INSTR
0001 1x01 0010 0100 0010 1000 0011 0x00 0011 1x11 0100 0100 0100 1100 0101 01xx
STEP_INSTR
0101 1100
STEP_REPLACE
0110 01xx
GET_CHIP_ID
0110 1000
Table 38: Debug Commands
Bit 7-4 3
Name
Description Not used Disable timers. Disable timer operation 0 Do not disable timers 1 Disable timers
timers_off
2
DMA_pause
DMA pause 0 Enable DMA transfers 1 Pause all DMA transfers
1
timer_suspend
Suspend timers. Timer operation is suspended for debug instructions and if a step instruction is a branch. If not suspended these instructions would result in an extra timer count during the clock cycle in which the branch is executed 0 Do not suspend timers 1 Suspend timers
0
sel_flash_info_page
Select flash information page in order to write flash lock bits. 0 Select flash main page 1 Select flash information page
Table 39: Debug Configuration
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Bit 7 Name chip_erase_done Description Flash chip erase done 0 Chip erase in progress 1 Chip erase done 6 pcon_idle PCON idle 0 CPU is running 1 CPU is idle (clock gated) 5 cpu_halted CPU halted 0 CPU running 1 CPU halted 4 power_mode_0 Power Mode 0 0 Power Mode 1-3 selected 1 Power Mode 0 selected 3 halt_status Halt status. Returns cause of last CPU halt 0 CPU was halted by HALT debug command 1 CPU was halted by software or hardware breakpoint 2 debug_locked Debug locked. Returns value of DBGLOCK bit 0 Debug interface is not locked 1 Debug interface is locked 1 oscillator_stable Oscillators stable. This bit represents the status of the CLKCON.XSOC_STB and CLKCON.HFRC_STB register bits. 0 Oscillators not stable 1 Oscillators stable 0 stack_overflow Stack overflow. This bit indicates when the CPU writes to DATA memory space at address 0xFF which is possibly a stack overflow 0 No stack overflow 1 Stack overflow
Table 40: Debug Status
12.9.7 Hardware Breakpoints The debug command SET_HW_BRKPNT is used to set a hardware breakpoint. The CC2510FX/CC2511Fx supports up to four hardware breakpoints. When a hardware breakpoint is enabled, it will compare the CPU address bus with the breakpoint.. When a match occurs, the CPU is halted. When issuing the SET_HW_BRKPNT, the external host must supply three data bytes that define the hardware breakpoint. The hardware breakpoint itself consists of 18 bits while three bits are used for control purposes. The format of the three data bytes for the SET_HW_BRKPNT command is as follows. The first data byte consists of the following: * * * * bits 7-5 bits 4-3 bit 2 : unused : breakpoint number; 0-3 : 1=enable, 0=disable
bits 1-0 : Memory bank bits. Bits 17-16 of hardware breakpoint.
The second data byte consists of bits 15-8 of the hardware breakpoint. The third data byte consists of bits 7-0 of the hardware breakpoint.
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12.9.8 Flash Programming Programming of the on-chip flash is performed via the debug interface. The external host must initially send instructions using the DEBUG_INSTR debug command to perform the flash programming with the Flash Controller as described in section 13.16. 12.10 RAM The CC2510FX/CC2511Fx contains static RAM. At power-on the contents of RAM is undefined. The RAM size is 1, 2 or 4 KB in total, mapped to the memory range 0xF000 - 0xFFFF. In the F8 and F16 versions parts of this memory range is not used. The memory locations 0xFDA2-0xFEFF consisting of 350 bytes in XDATA memory that do not retain data when power modes PM2/3 is entered. All other RAM memory locations are retained in all power modes. Refer to Table 28 for a description of the SRAM memory map. 12.11 Flash Memory The on-chip flash memory consists of 32768 bytes. The flash memory is primarily intended to hold program code. The flash memory has the following features: * * * Flash page erase time: 20 ms Flash chip (mass) erase time: 20 ms Flash write time (16 bit word): 20 s
4
* *
Data retention4:100 years Program/erase endurance: Minimum 1,000 cycles
The flash memory consists of the Flash Main Page which is where the CPU reads program code and data. The flash memory also contains a Flash Information Page which contains the Flash Lock Bits. The Flash Information Page and hence the Lock Bits is only accessed by first selecting this page through the Debug Interface. The Flash Controller (see section 13.16) is used to write and erase the contents of the flash memory. When the CPU reads instructions from flash memory, it fetches the next instruction through a cache. The instruction cache is provided mainly to reduce power consumption by reducing the amount of time the flash memory itself is accessed. The use of the instruction cache may be disabled with the MEMCTR.CACHDIS register bit. 12.12 Memory Arbiter The CC2510FX/CC2511Fx includes a memory arbiter which handles CPU and DMA access to all memory space. A control register MEMCTR is used to control the flash cache. The MEMCTR register is described below.
At room temperature
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MEMCTR (0xC7) - Memory Arbiter Control
Bit 7:6 5:4 3:2 1 Name Reset 00 01 00 0 R/W R0 R/W R0 R/W Description Not used Not used. Must always be set to 01. Not used Flash cache disable. Invalidates contents of instruction cache and forces all instruction read accesses to read straight from flash memory. Disabling will increase power consumption and is provided for debug purposes. 0 1 0 Cache enabled Cache disabled
CACHDIS
PREFDIS
0
R/W
Flash pre-fetch disable. Disables pre-fetching of cache read data. Disabling will reduce performance and is provided for debug purposes. 0 1 Flash pre-fetch enabled Flash pre-fetch disabled
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13 Peripherals
In following sub-sections, each CC2510FX/CC2511Fx peripheral is described in detail. The CC2510FX/CC2511Fx has four timers. These timers all run on the tick frequency given by the Power Management Controller register CLKCON.TICKSPD. 13.1 I/O ports Note: Note: P0_6 and P0_7 does not exist on CC2511Fx. The CC2511Fx has 19 digital input/output pins available and the ADC inputs 6 and 7 cannot be used. Apart from this, all information in this section applies to both CC2511Fx and CC2510FX. The CC2510FX has 21 digital input/output pins that can be configured as general purpose digital I/O or as peripheral I/O signals connected to the ADC, Timers, I2S or USART peripherals. The usage of the I/O ports is fully configurable from user software through a set of configuration registers. The I/O ports have the following key features: * * * * 21 digital input/output pins General purpose I/O or peripheral I/O Pull-up or pull-down capability on inputs, except P1_0 and P1_1. External interrupt capability the To use a port as a general purpose I/O pin the pin must first be configured. The registers PxSEL where x is the port number 0-2 are used to configure each pin in a port either as a general purpose I/O pin or as a peripheral I/O signal. By default, after a reset, all digital input/output pins are configured as generalpurpose I/O pins. By default, all general-purpose I/O pins are configured as inputs. To change the direction of a port pin, at any time, the registers PxDIR are used to set each port pin to be either an input or an output. Thus by setting the appropriate bit within PxDIR to 1, the corresponding pin becomes an output. When reading the port registers P0, P1 and P2, the logic values on the input pins are returned regardless of the pin configuration. This does not apply during the execution of read-modify-write instructions. The readmodify-write instructions when operating on a port registers are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a port register P0, P1 or P2. For these read-modify-write instructions, the value of the register, not the value on the pin, is read, modified, and written back to the port register. When used as an input, the general purpose I/O port pins can be configured to have a pullup, pull-down or tri-state mode of operation. By default, after a reset, inputs are configured as inputs with pull-up. To deselect the pullup/pull-down function on an input the appropriate bit within the PxINP must be set to 1. The I/O port pins P1_0 and P1_1 do not have pull-up/pull-down capability. In power modes PM1, PM2 and PM3 the I/O pins retain the I/O mode and output value (if applicable) that was set when PM1/2/3 was entered. 13.1.2 General Purpose I/O Interrupts General purpose I/O pins configured as inputs can be used to generate interrupts. The interrupts can be configured to trigger on either a rising or falling edge of the external signal. Each of the P0, P1 and P2 ports have separate interrupt enable bits common for all bits within the port located in the IEN1-2 registers as follows:
The external interrupt capability is available on all 21 I/O pins. Thus, external devices may generate interrupts if required. The external interrupt feature can also be used to wake up from sleep modes. 13.1.1 General Purpose I/O When used as general purpose I/O, the pins are organized as three 8-bit ports, ports 0-2, denoted P0, P1 and P2. P0 and P1 are complete 8-bit wide ports while P2 has only five usable bits (P2_0 to P2_4). All ports are both bit- and byte addressable through the SFR registers P0, P1 and P2. Each port pin can individually be set to operate as a general purpose I/O or as a peripheral I/O. The output drive strength is 4 mA on all outputs, except for the two high-drive outputs, P1_0 and P1_1, which each have 20 mA output drive strength.
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* * * IEN1.P0IE : P0 interrupt enable IEN2.P1IE : P1 interrupt enable IEN2.P2IE : P2 interrupt enable 13.1.3 General Purpose I/O DMA When used as general purpose I/O pins, the P0 and P1 ports are each associated with one DMA trigger. These DMA triggers are IOC_0 for P0 and IOC_1 for P1 as shown in Table 42 on page 90. The IOC_0 or IOC_1 DMA trigger is activated when an input transition occurs on one of the P0 or P1 pins respectively. Note that only input transitions on pins configured as general purpose I/O inputs, will produce the DMA trigger. 13.1.4 Peripheral I/O This section describes how the digital input/output pins are configured as peripheral I/Os. For each peripheral unit that can interface with an external system through the digital input/output pins, a description of how peripheral I/Os are configured is given in the following sub-sections. In general, setting the appropriate PxSEL bits to 1 is required to select peripheral I/O function on a digital I/O pin. Note that peripheral units have two alternative locations for their I/O pins, refer to Table 41. The location to be used is selected by writing to PERCFG. It is possible to set PERCFG so that several peripherals are assigned to the same port pins. In such cases a set of peripheral priority control bits select the order of precedence between up to two peripherals at a time, when these are assigned to the same port pins.
In addition to these common interrupt enables, the bits within each port have interrupt enables located in I/O port SFR registers. Each bit within P1 has an individual interrupt enable. In P0 the low-order nibble and the high-order nibble have their individual interrupt enables. For the P2_0 - P2_4 inputs there is a common interrupt enable. When an interrupt condition occurs on one of the general purpose I/O pins, the corresponding interrupt status flag in the P0P2 interrupt flag registers, P0IFG , P1IFG or P2IFG will be set to 1. The interrupt status flag is set regardless of whether the pin has its interrupt enable set. When an interrupt is serviced the interrupt status flag is cleared by writing a 0 to that flag. The SFR registers used for I/O interrupts are described in section 12.7 on page 49. The registers are summarized below: * * * * * P1IEN : P1 interrupt enables PICTL : P0/P2 interrupt enables and P0-2 edge configuration P0IFG : P0 interrupt flags P1IFG : P1 interrupt flags P2IFG : P2 interrupt flags
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Table 41: Peripheral I/O Pin Mapping
Periphery / Function ADC USART0 Alt 1 SPI Alt. 2
TX RX TX MI M0 C SS MI RX TX RX 2 1 0 0 1 1 0 1 0 1
CK WS RX TX
CK WS RX TX
P0 7
1
P1 6
1
P2 6 5 4 3 2 1 0 4 3 2 1 0
5
A5 C
4
A4 SS
3
A3 M0
2
A2 MI
1
A1
0
A0
7
A7
A6
MO
MI
C
SS
USART0 Alt. 1 UART
Alt. 2
RX
USART1 Alt.1 SPI Alt. 2
M0
C
SS
USART1 Alt. 1
UART
Alt. 2
TX
TIMER1 Alt.1 Alt. 2 TIMER3 Alt.1 Alt. 2 TIMER4 Alt.1 Alt. 2 I2S Alt. 1 Alt. 2 32.768kHz XOSC DEBUG
1
2
0
0
Q2
Q1
D C
D D
1
This pin is only found on CC2510FX ,it does not exist on CC2511Fx. * SS : SSN
13.1.4.1 USART0 The SFR register bit PERCFG.U0CFG selects whether to use alternative 1 or alternative 2 locations. Note that if both USARTs are used, they must be on different ports, i.e. one on P0 and one on P1. This applies both in UART and SPI mode. In Table 41, the USART0 signals are shown as follows: UART: * * SPI: * * * MI : MISO MO : MOSI C : SCK RX : RXDATA TX : TXDATA
P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to port 0, i.e. the situation when several peripherals are assigned to the same pin locations. When set to 00, USART0 has precedence. Note that if UART mode is selected, USART1 or timer 1 will have precedence to use ports P0_4 and P0_5. P2SEL.PRI3P1 and P2SEL.PRI0P1 select the order of precedence when assigning several peripherals to port 1. USART0 has precedence when both are set to 0. Note that if UART mode is selected, timer 1 or timer 3 will have precedence to use ports P1_2 and P1_3. 13.1.4.2 USART1 The SFR register bit PERCFG.U1CFG selects whether to use alternative 1 or alternative 2
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locations. Note that if both USARTs are used, they must be on different ports, i.e. one on P0 and one on P1. This applies both in UART and SPI mode. 13.1.4.4 Timer 3 PERCFG.T3CFG selects whether to alternative 1 or alternative 2 locations. use
In Table 41, the Timer 3 signals are shown as the following: In Table 41, the USART1 signals are shown as follows: * * SPI: * * * * MI : MISO MO : MOSI C : SCK SS : SSN RX : RXDATA TX : TXDATA * * 0 : Channel 0 capture/compare pin 1 : Channel 1 capture/compare pin
P2SEL.PRI2P1 selects the order of precedence when assigning several peripherals to port 1. The timer 3 channels have precedence when the bit is set. 13.1.4.5 Timer 4 PERCFG.T4CFG selects whether to alternative 1 or alternative 2 locations. use
In Table 41, the Timer 4 signals are shown as the following: * 0 : Channel 0 capture/compare pin 1 : Channel 1 capture/compare pin *
P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to port 0. When set to 01, USART1 has precedence. Note that if UART mode is selected, USART0 or timer 1 will have precedence to use ports P0_2 and P0_3. P2SEL.PRI3P1 and P2SEL.PRI2P1 select the order of precedence when assigning several peripherals to port 1. USART1 has precedence when the former is set to 1 and the latter is set to 0. Note that if UART mode is selected, USART0 or timer 3 will have precedence to use ports P2_4 and P2_5. 13.1.4.3 Timer 1 PERCFG.T1CFG selects whether to alternative 1 or alternative 2 locations. use
P2SEL.PRI1P1 selects the order of precedence when assigning several peripherals to port 1. The timer 4 channels have precedence when the bit is set. 13.1.4.6 I2S The I2S configuration register bit I2SCFG1.IOLOC selects whether to use alternative 1 or alternative 2 locations. In Table 41, the follows: * * * * I2S signals are shown as
CK : Continous Serial Clock (SCK) WS : Word Select RX : Serial Data In TX : Serial Data Out
In Table 41, the Timer 1 signals are shown as the following: * * * 0 : Channel 0 capture/compare pin 1 : Channel 1 capture/compare pin 2 : Channel 2 capture/compare pin
13.1.5 ADC When using the ADC in an application, the Port 0 pins used must be configured as ADC inputs. Up to eight ADC inputs can be used. The port pins are mapped to the ADC inputs so that P0_7 - P0_0 corresponds to AIN7AIN0. To configure a Port 0 pin to be used as an ADC input the corresponding bit in the ADCCFG register must be set to 1. The default values in this register select the Port 0 pins as non-ADC input i.e. digital input/outputs. The settings in the ADCCFG register override the settings in P0SEL.
P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to port 0. When set to 10 or 11 the timer 1 channels have precedence. P2SEL.PRI1P1 and P2SEL.PRI0P1 select the order of precedence when assigning several peripherals to port 1. The timer 1 channels have precedence when the former is set low and the latter is set high.
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The ADC can be configured to use the general-purpose I/O pin P2_0 as an external trigger to start conversions. P2_0 must be configured as a general-purpose I/O in input mode, when being used for ADC external trigger. Refer to section 13.7 on page 127 for a detailed description of use of the ADC. 13.1.6 Debug interface Port pins P2_1 and P2_2 are used for debug data and clock signals, respectively. These are shown as DD (debug data) and DC (debug clock) in Table 41. When the debug interface is in use, P2DIR should select these pins as inputs. The state of P2SEL is overridden by the debug interface. Also, the direction is overridden when the chip changes the direction to supply the external host with data. 13.1.7 32.768 kHz XOSC input Ports P2_3 and P2_4 are used to connect an external 32.768 kHz crystal. These port pins will be used by the 32.768 kHz crystal oscillator when CLKCON.OSC32K is low, regardless of register settings. The port pins will be set in analog mode when CLKCON.OSC32K is low. 13.1.8 Unused I/O pins Unused I/O pins should have a defined level and not be left floating. One way to do this is to leave the pin unconnected and configure the pin as a general purpose I/O input with pull-up resistor. This is also the state of all pins during reset (except P1_0 and P1_1 which do not have pull-up/pull-down resistors). Alternatively the pin can be configured as a general purpose I/O output. In both cases the pin should not be connected directly to VDD or GND in order to avoid excessive power consumption. 13.1.9 IOC registers The registers for the IO ports are described in this section. The registers are: * * * * * * * * * * * * * * * * * * * P0 Port 0 P1 Port 1 P2 Port 2 PERCFG Peripheral control register ADCCFG register ADC input configuration
P0SEL Port 0 function select register P1SEL Port 1 function select register P2SEL Port 2 function select register P0DIR Port 0 direction register P1DIR Port 1 direction register P2DIR Port 2 direction register P0INP Port 0 input mode register P1INP Port 1 input mode register P2INP Port 2 input mode register P0IFG Port 0 interrupt status flag register P1IFG Port 1 interrupt status flag register P2IFG Port 2 interrupt status flag register PICTL Interrupt register mask and edge
P1IEN Port 1 interrupt mask register
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P0 (0x80) - Port 0
Bit Name Reset R/W Description
7:0
P0[7:0]
0xFF
R/W
Port 0. General purpose I/O port. Bit-addressable.
P1 (0x90) - Port 1
Bit Name Reset R/W Description
7:0
P1[7:0]
0xFF
R/W
Port 1. General purpose I/O port. Bit-addressable.
P2 (0xA0) - Port 2
Bit Name Reset R/W Description
7:0 4:0
P2[4:0]
000 0x1F
R0 R/W
Not used Port 2. General purpose I/O port. Bit-addressable.
PERCFG (0xF1) - Peripheral Control
Bit 7 6 Name Reset 0 0 R/W R0 R/W Description Not used Timer 1 I/O location 0 1 5 Alternative 1 location Alternative 2 location
T1CFG
T3CFG
0
R/W
Timer 3 I/O location 0 1 Alternative 1 location Alternative 2 location
4
T4CFG
0
R/W
Timer 4 I/O location 0 1 Alternative 1 location Alternative 2 location
3:2 1
U1CFG
00 0
R0 R/W
Not used USART1 I/O location 0 1 Alternative 1 location Alternative 2 location
0
U0CFG
0
R/W
USART0 I/O location 0 1 Alternative 1 location Alternative 2 location
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ADCCFG (0xF2) - ADC Input Configuration
Bit 7:0 Name Reset 0x00 R/W R/W Description ADC input configuration. ADCCFG[7:0] shall select P0_7 - P0_0 as ADC inputs AIN7 - AIN0 0 1 ADC input disabled ADC input enabled
ADCCFG[7:0]
P0SEL (0xF3) - Port 0 Function Select
Bit 7 Name Reset 0 R/W R/W Description P0_7 function select 0 1 6 General purpose I/O Peripheral function
SELP0_7
SELP0_6
0
R/W
P0_6 function select 0 1 General purpose I/O Peripheral function
5
SELP0_5
0
R/W
P0_5 function select 0 1 General purpose I/O Peripheral function
4
SELP0_4
0
R/W
P0_4 function select 0 1 General purpose I/O Peripheral function
3
SELP0_3
0
R/W
P0_3 function select 0 1 General purpose I/O Peripheral function
2
SELP0_2
0
R/W
P0_2 function select 0 1 General purpose I/O Peripheral function
1
SELP0_1
0
R/W
P0_1 function select 0 1 General purpose I/O Peripheral function
0
SELP0_0
0
R/W
P0_0 function select 0 1 General purpose I/O Peripheral function
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P1SEL (0xF4) - Port 1 Function Select
Bit 7 Name Reset 0 R/W R/W Description P1_7 function select 0 1 6 General purpose I/O Peripheral function
SELP1_7
SELP1_6
0
R/W
P1_6 function select 0 1 General purpose I/O Peripheral function
5
SELP1_5
0
R/W
P1_5 function select 0 1 General purpose I/O Peripheral function
4
SELP1_4
0
R/W
P1_4 function select 0 1 General purpose I/O Peripheral function
3
SELP1_3
0
R/W
P1_3 function select 0 1 General purpose I/O Peripheral function
2
SELP1_2
0
R/W
P1_2 function select 0 1 General purpose I/O Peripheral function
1
SELP1_1
0
R/W
P1_1 function select 0 1 General purpose I/O Peripheral function
0
SELP1_0
0
R/W
P1_0 function select 0 1 General purpose I/O Peripheral function
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P2SEL (0xF5) - Port 2 Function Select
Bit 7 6 Name Reset 0 0 R/W R0 R/W Description Not used Port 1 peripheral priority control. These bits shall determine the order of priority in the case when PERCFG assigns USART0 and USART1 to the same pins. 0 1 5 USART0 has priority USART1 has priority
PRI3P1
PRI2P1
0
R/W
Port 1 peripheral priority control. These bits shall determine the order of priority in the case when PERCFG assigns USART1 and timer 3 to the same pins. 0 1 USART1 has priority Timer 3 has priority
4
PRI1P1
0
R/W
Port 1 peripheral priority control. These bits shall determine the order of priority in the case when PERCFG assigns timer 1 and timer 4 to the same pins. 0 1 Timer 1 has priority Timer 4 has priority
3
PRI0P1
0
R/W
Port 1 peripheral priority control. These bits shall determine the order of priority in the case when PERCFG assigns USART0 and timer 1 to the same pins. 0 1 USART0 has priority Timer 1 has priority
2
SELP2_4
0
R/W
P2_4 function select 0 1 General purpose I/O Peripheral function
1
SELP2_3
0
R/W
P2_3 function select 0 1 General purpose I/O Peripheral function
0
SELP2_0
0
R/W
P2_0 function select 0 1 General purpose I/O Peripheral function
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P0DIR (0xFD) - Port 0 Direction
Bit 7 Name Reset 0 R/W R/W Description P0_7 I/O direction 0 1 6 Input Output
DIRP0_7
DIRP0_6
0
R/W
P0_6 I/O direction 0 1 Input Output
5
DIRP0_5
0
R/W
P0_5 I/O direction 0 1 Input Output
4
DIRP0_4
0
R/W
P0_4 I/O direction 0 1 Input Output
3
DIRP0_3
0
R/W
P0_3 I/O direction 0 1 Input Output
2
DIRP0_2
0
R/W
P0_2 I/O direction 0 1 Input Output
1
DIRP0_1
0
R/W
P0_1 I/O direction 0 1 Input Output
0
DIRP0_0
0
R/W
P0_0 I/O direction 0 1 Input Output
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P1DIR (0xFE) - Port 1 Direction
Bit 7 Name Reset 0 R/W R/W Description P1_7 I/O direction 0 1 6 Input Output
DIRP1_7
DIRP1_6
0
R/W
P1_6 I/O direction 0 1 Input Output
5
DIRP1_5
0
R/W
P1_5 I/O direction 0 1 Input Output
4
DIRP1_4
0
R/W
P1_4 I/O direction 0 1 Input Output
3
DIRP1_3
0
R/W
P1_3 I/O direction 0 1 Input Output
2
DIRP1_2
0
R/W
P1_2 I/O direction 0 1 Input Output
1
DIRP1_1
0
R/W
P1_1 I/O direction 0 1 Input Output
0
DIRP1_0
0
R/W
P1_0 I/O direction 0 1 Input Output
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P2DIR (0xFF) - Port 2 Direction
Bit 7:6 Name Reset 0 R/W R/W Description Port 0 peripheral priority control. These bits shall determine the order of priority in the case when PERCFG assigns several peripherals to the same pins 00 01 10 11 5 4 USART0 - USART1 USART1 - USART0 Timer 1 channels 0 and 1 - USART1 Timer 1 channel 2 - USART0
PRIP0[1:0]
DIRP2_4
0 0
R0 R/W
Not used P2_4 I/O direction 0 1 Input Output
3
DIRP2_3
0
R/W
P2_3 I/O direction 0 1 Input Output
2
DIRP2_2
0
R/W
P2_2 I/O direction 0 1 Input Output
1
DIRP2_1
0
R/W
P2_1 I/O direction 0 1 Input Output
0
DIRP2_0
0
R/W
P2_0 I/O direction 0 1 Input Output
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P0INP (0x8F) - Port 0 Input Mode
Bit 7 Name Reset 0 R/W R/W Description P0_7 I/O input mode 0 1 6 Pull-up / pull-down Tristate
MDP0_7
MDP0_6
0
R/W
P0_6 I/O input mode 0 1 Pull-up / pull-down Tristate
5
MDP0_5
0
R/W
P0_5 I/O input mode 0 1 Pull-up / pull-down Tristate
4
MDP0_4
0
R/W
P0_4 I/O input mode 0 1 Pull-up / pull-down Tristate
3
MDP0_3
0
R/W
P0_3 I/O input mode 0 1 Pull-up / pull-down Tristate
2
MDP0_2
0
R/W
P0_2 I/O input mode 0 1 Pull-up / pull-down Tristate
1
MDP0_1
0
R/W
P0_1 I/O input mode 0 1 Pull-up / pull-down Tristate
0
MDP0_0
0
R/W
P0_0 I/O input mode 0 1 Pull-up / pull-down Tristate
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CC2510FX / CC2511Fx
P1INP (0xF6) - Port 1 Input Mode
Bit 7 Name Reset 0 R/W R/W Description P1_7 I/O input mode 0 1 6 Pull-up / pull-down Tristate
MDP1_7
MDP1_6
0
R/W
P1_6 I/O input mode 0 1 Pull-up / pull-down Tristate
5
MDP1_5
0
R/W
P1_5 I/O input mode 0 1 Pull-up / pull-down Tristate
4
MDP1_4
0
R/W
P1_4 I/O input mode 0 1 Pull-up / pull-down Tristate
3
MDP1_3
0
R/W
P1_3 I/O input mode 0 1 Pull-up / pull-down Tristate
2
MDP1_2
0
R/W
P1_2 I/O input mode 0 1 Pull-up / pull-down Tristate
1:0
-
00
R0
Not used
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P2INP (0xF7) - Port 2 Input Mode
Bit 7 Name Reset 0 R/W R/W Description Port 2 pull-up/down select. Selects function for all Port 2 pins configured as pull-up/pull-down inputs. 0 1 6 Pull-up Pull-down
PDUP2
PDUP1
0
R/W
Port 1 pull-up/down select. Selects function for all Port 1 pins configured as pull-up/pull-down inputs. 0 1 Pull-up Pull-down
5
PDUP0
0
R/W
Port 0 pull-up/down select. Selects function for all Port 0 pins configured as pull-up/pull-down inputs. 0 1 Pull-up Pull-down
4
MDP2_4
0
R/W
P2_4 I/O input mode 0 1 Pull-up / pull-down Tristate
3
MDP2_3
0
R/W
P2_3 I/O input mode 0 1 Pull-up / pull-down Tristate
2
MDP2_2
0
R/W
P2_2 I/O input mode 0 1 Pull-up / pull-down Tristate
1
MDP2_1
0
R/W
P2_1 I/O input mode 0 1 Pull-up / pull-down Tristate
0
MDP2_0
0
R/W
P2_0 I/O input mode 0 1 Pull-up / pull-down Tristate
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P0IFG (0x89) - Port 0 Interrupt Status Flag
CC2510FX:
Bit 7:0 Name Reset 0x00 R/W R/W0 Description Port 0, inputs 7 to 0 interrupt status flags. When an input port pin has an interrupt request pending, the corresponding flag bit will be set.
P0IF[7:0]
CC2511Fx:
Bit 7 6 5:0 Name Reset 0 0 0x00 R/W R/W0 R0 R/W0 Description USB Resume detected during suspend. Not used Port 0, inputs 7 to 0 interrupt status flags. When an input port pin has an interrupt request pending, the corresponding flag bit will be set.
USB_RESUME P0IF[5:0]
P1IFG (0x8A) - Port 1 Interrupt Status Flag
Bit 7:0 Name Reset 0x00 R/W R/W0 Description Port 1, inputs 7 to 0 interrupt status flags. When an input port pin has an interrupt request pending, the corresponding flag bit will be set.
P1IF[7:0]
P2IFG (0x8B) - Port 2 Interrupt Status Flag
Bit 7:5 4:0 Name Reset 000 0x00 R/W R0 R/W0 Description Not used. Port 2, inputs 4 to 0 interrupt status flags. When an input port pin has an interrupt request pending, the corresponding flag bit will be set.
P2IF[4:0]
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PICTL (0x8C) - Port Interrupt Control
Bit 7 6 5 Name Reset 0 0 0 R/W R0 R/W R/W Description Not used Reserved. Write 0 Port 2, inputs 4 to 0 interrupt enable. This bit enables interrupt requests for the port 2 inputs 4 to 0. 0 1 4 Interrupts are disabled Interrupts are enabled
P2IEN
P0IENH
0
R/W
Port 0, inputs 7 to 4 interrupt enable. This bit enables interrupt requests for the port 0 inputs 7 to 4. 0 1 Interrupts are disabled Interrupts are enabled
3
P0IENL
0
R/W
Port 0, inputs 3 to 0 interrupt enable. This bit enables interrupt requests for the port 0 inputs 3 to 0. 0 1 Interrupts are disabled Interrupts are enabled
2
P2ICON
0
R/W
Port 2, inputs 4 to 0 interrupt configuration. This bit selects the interrupt request condition for all port 2 inputs 0 1 Rising edge on input gives interrupt Falling edge on input gives interrupt
1
P1ICON
0
R/W
Port 1, inputs 7 to 0 interrupt configuration. This bit selects the interrupt request condition for all port 1 inputs 0 1 Rising edge on input gives interrupt Falling edge on input gives interrupt
0
P0ICON
0
R/W
Port 0, inputs 7 to 0 interrupt configuration. This bit selects the interrupt request condition for all port 0 inputs. For CC2511Fx this bit must not be set to 1 when USB is used, since the internal USB resume interrupt mapped to P0[7] uses rising edge. 0 1 Rising edge on input gives interrupt Falling edge on input gives interrupt
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P1IEN (0x8D) - Port 1 Interrupt Mask
Bit 7 Name Reset 0 R/W R/W Description Port P1_7 interrupt enable 0 1 6 Interrupts are disabled Interrupts are enabled
P1_7IEN
P1_6IEN
0
R/W
Port P1_6 interrupt enable 0 1 Interrupts are disabled Interrupts are enabled
5
P1_5IEN
0
R/W
Port P1_5 interrupt enable 0 1 Interrupts are disabled Interrupts are enabled
4
P1_4IEN
0
R/W
Port P1_4 interrupt enable 0 1 Interrupts are disabled Interrupts are enabled
3
P1_3IEN
0
R/W
Port P1_3 interrupt enable 0 1 Interrupts are disabled Interrupts are enabled
2
P1_2IEN
0
R/W
Port P1_2 interrupt enable 0 1 Interrupts are disabled Interrupts are enabled
1
P1_1IEN
0
R/W
Port P1_1 interrupt enable 0 1 Interrupts are disabled Interrupts are enabled
0
P1_0IEN
0
R/W
Port P1_0 interrupt enable 0 1 Interrupts are disabled Interrupts are enabled
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13.2 DMA Controller The CC2510FX/CC2511Fx includes a direct memory access (DMA) controller, which can be used to relieve the 8051 CPU core of handling data movement operations. Thus the CC2510FX/CC2511Fx can achieve high overall performance with good power efficiency. The DMA controller can move data from a peripheral unit such as ADC or RF transceiver to memory with minimum CPU intervention. The DMA controller module coordinates all DMA transfers, ensuring that DMA requests are prioritized appropriately relative to each other and CPU memory access. The DMA controller contains a number of programmable DMA channels for memory-to-memory data movement. The DMA controller controls data movement over the entire XDATA memory space. Since all the SFR registers (except some internal registers) are mapped into the DMA memory space these flexible DMA channels can be used to unburden the 8051 in innovative ways, e.g. feed a USART and I2S with data from memory, periodically transfer samples between ADC and memory, transfer data to and from USB FIFOs (CC2511Fx) etc. Use of the DMA can also reduce system power consumption by letting the CPU run on a lower frequency (CLKCON.CLKSPD) . The main features of the DMA controller are as follows: * * * * Five independent DMA channels Three configurable levels of DMA channel priority 30 configurable transfer trigger events Independent control of source and destination address * * Single, block and repeated transfer modes Supports variable transfer length by including the length field in the transfer data Can operate in either word-size or byte-size mode
*
13.2.1 DMA Operation There are five DMA channels available in the DMA controller numbered channel 0 to channel 4. Each DMA channel can move data from one place within the DMA memory space to another. In order to use a DMA channel it must first be configured as described in sections 13.2.2 and 13.2.3. Once a DMA channel has been configured it must be armed before any transfers are allowed to be initiated. A DMA channel is armed by setting the appropriate bit in the DMA Channel Arm register DMAARM. When a DMA channel is armed a transfer will begin when the configured DMA trigger event occurs. There are 30 possible DMA trigger events, e.g. UART transfer, Timer overflow etc. The trigger event to be used by a DMA channel is set by the DMA channel configuration. The DMA trigger events are listed in Table 42. In addition to starting a DMA transfer through the DMA trigger events, the user software may force a DMA transfer to begin by setting the corresponding DMAREQ bit. Figure 12 shows the DMA state diagram.
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Figure 12: DMA Operation
13.2.2 DMA Configuration Parameters Setup and control of the DMA operation is performed by the user software. This section
describes the parameters that must be configured before a DMA channel can be used. Section 13.2.3 on page 88 describes
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how the parameters are set up in software and passed to the DMA controller. The behavior of each of the five DMA channels is configured with the following parameters: Source address. The first address from which the DMA channel should read data. Destination address. The first address to which the DMA channel should write the data read from the source address. The user must ensure that the destination is writable. Transfer count. The number of transfers to perform before rearming or disarming the DMA channel and alerting the CPU with an interrupt request. The length can be defined in the configuration or it can be defined as described next as VLEN setting. VLEN setting. The DMA channel is capable of variable length transfers using the first byte or word at the source address to set the transfer length. When doing this, various options regarding how to count number of bytes to transfer are available. Priority. The priority of the DMA transfers for the DMA channel in respect to the CPU and other DMA channels and access ports. Trigger event. All DMA transfers are initiated by so-called DMA trigger events. This trigger either starts a DMA block transfer or a single DMA transfer. Source and Destination Increment. The source and destination addresses can be controlled to increment, decrement, or not change, in order to give good flexibility for various types of transfers. Transfer mode. The transfer mode determines whether the transfer should be a single transfer or a block transfer, or repeated versions of these. Byte or word transfers. Determines whether each DMA transfer should be 8-bit (byte) or 16-bit (word). Interrupt Mask. An interrupt request is generated upon completion of the DMA transfer. The interrupt mask bit controls if the interrupt generation is enabled or disabled. M8: Decide whether to use seven or eight bits of length byte for transfer length. Only applicable when doing byte transfers. A detailed description of the configuration parameters is given in the following sections. 13.2.2.1 Source Address The address of the location in XDATA memory space where the DMA channel shall start to read data for the transfer. 13.2.2.2 Destination Address The address of the location in XDATA memory space where the DMA channel shall start to write transfer data. The user must ensure that the destination is writable. 13.2.2.3 Transfer Count The number of bytes/words needed to be transferred for the DMA transfer to be complete. When the transfer count is reached, the DMA controller rearms or disarms the DMA channel (depending on transfer mode) and alerts the CPU with an interrupt request. The transfer count can be defined in the configuration or it can be defined as a variable length described in the next section. 13.2.2.4 VLEN Setting The DMA channel is capable of using the first byte or word (for word, bits 12:0 are used) in source data as the transfer length. This allows variable length transfers. When using variable length transfer, various options regarding how to count number of bytes to transfer is given. In any case, the LEN setting is used as maximum transfer count. Note that the M8 bit is only used when byte size transfers are chosen. Options are: 1. Default : Transfer number of bytes/words commanded by first byte/word + 1 (transfers length byte/word, and then as many bytes/words as dictated by length byte/word) 2. Transfer number of bytes/words commanded by first byte/word 3. Transfer number of bytes/words commanded by first byte/word + 2 (transfers length byte/word, and then as many bytes/words as dictated by length byte/word + 1) 4. Transfer number of bytes/words commanded by first byte/word + 3 (transfers length byte/word, and then as many bytes/words as dictated by length byte/word + 2)
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byte/word n+2 byte/word n+1 byte/word n byte/word n-1 byte/word n byte/word n-1 byte/word n byte/word n-1 byte/word n+1 byte/word n byte/word n-1
byte/word 3 byte/word 2 byte/word 1 LENGTH=n
byte/word 3 byte/word 2 byte/word 1 LENGTH=n
byte/word 3 byte/word 2 byte/word 1 LENGTH=n
byte/word 3 byte/word 2 byte/word 1 LENGTH=n
VLEN=001
VLEN=010
VLEN=011
VLEN=100
Figure 13: Variable Length (VLEN) Transfer Options
13.2.2.5 Trigger Event Each DMA channel can be set up to sense on a single trigger. This field determines which trigger the DMA channel shall sense. In addition to the configured trigger, a DMA channel can always be triggered by setting its designated DMAREQ.DMAREQx flag. The DMA trigger sources are described in Table 42 on page 90. 13.2.2.6 Source and Destination Increment When the DMA channel is armed or rearmed the source and destination addresses are transferred to internal address pointers. The possibilities for address increment are : * Increment by zero. The address pointer shall remain fixed after each transfer. Increment by one. The address pointer shall increment one count after each transfer. Increment by two. The address pointer shall increment two counts after each transfer. Decrement by one. The address pointer shall decrement one count after each transfer.
13.2.2.7 DMA Transfer Mode The transfer mode determines how the DMA channel behaves when it starts transferring data. There are four transfer modes described below: Single. On a trigger a single DMA transfer occurs and the DMA channel awaits the next trigger. After the number of transfers specified by the transfer count are completed, the CPU is notified and the DMA channel is disarmed. Block. On a trigger the number of DMA transfers specified by the transfer count is performed as quickly as possible, after which the CPU is notified and the DMA channel is disarmed. Repeated single. On a trigger a single DMA transfer occurs and the DMA channel awaits the next trigger. After the number of transfers specified by the transfer count are completed, the CPU is notified and the DMA channel is rearmed. Repeated block. On a trigger the number of DMA transfers specified by the transfer count is performed as quickly as possible, after which the CPU is notified and the DMA channel is rearmed. 13.2.2.8 DMA Priority A DMA priority is associated with each DMA channel. The DMA priority is used to determine the winner in the case of multiple
*
*
*
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simultaneous internal memory requests, and whether the DMA memory access should have priority or not over a simultaneous CPU memory access. In case of an internal tie, a round-robin scheme is used to ensure access for all. There are three levels of DMA priority: High. Highest internal priority. DMA access will always prevail over CPU access. Normal. Second highest internal priority. Guarantees that DMA access prevails over CPU on at least every second try. Low. Lowest internal priority. DMA access will always defer to a CPU access. 13.2.2.9 Byte or Word transfers Determines whether 8-bit (byte) or 16-bit (word) are done. 13.2.2.10 Interrupt mask Upon completing a DMA transfer, the channel can generate an interrupt to the processor. This bit will mask the interrupt. 13.2.2.11 Mode 8 setting This field determines whether to use seven or 8 bits of length byte for transfer length. Only applicable when doing byte transfers. 13.2.3 DMA Configuration Setup The DMA channel parameters such as address mode, transfer mode and priority described in the previous section have to be configured before a DMA channel can be armed and activated. The parameters are not configured directly through SFR registers, but instead they are written in a special DMA configuration data structure in memory. Each DMA channel in use requires its own DMA configuration data structure. The DMA configuration data structure consists of eight bytes and is described in section 13.2.6 A DMA configuration data structure may reside at any location in XDATA decided upon by the user software, and the address location is
MOV DMAARM, #0x03
passed to the DMA controller through a set of SFRs DMAxCFGH:DMAxCFGL, Once a channel has been armed, the DMA controller will read the configuration data structure for that channel, given by the address in DMAxCFGH:DMAxCFGL. It is important to note that the method for specifying the start address for the DMA configuration data structure differs between DMA channel 0 and DMA channels 1-4 as follows: DMA0CFGH:DMA0CFGL gives the start address for DMA channel 0 configuration data structure. DMA1CFGH:DMA1CFGL gives the start address for DMA channel 1 configuration data structure followed by channel 2-4 configuration data structures. Thus the DMA controller expects the DMA configuration data structures for DMA channels 1-4 to lie in a contiguous area in memory, starting at the address held in DMA1CFGH:DMA1CFGL and consisting of 32 bytes. 13.2.4 Stopping DMA Transfers Ongoing DMA transfer or armed DMA channels will be aborted using the DMAARM register to disarm the DMA channel. One or more DMA channels are aborted by writing the following to the DMAARM register. * * Writing a 1 to DMAARM.ABORT, and at the same time, Select which DMA channels to abort by setting the corresponding, DMAARM.DMAARMx bits.
An example of DMA channel arm and disarm is shown in Figure 14.
; arm DMA channel 0 and 1
MOV DMAARM, #0x81
; disarm DMA channel 0, ; channel 1 is still armed
Figure 14: DMA arm/disarm example
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13.2.5 DMA Interrupts Each DMA channel can be configured to generate an interrupt to the CPU upon completing a DMA transfer. This is accomplished with the IRQMASK bit in the channel configuration. The corresponding interrupt flag in the DMAIRQ SFR register will be set when the interrupt is generated. Regardless of the IRQMASK bit in the channel configuration, the interrupt flag will be set upon DMA channel complete. Thus software should always check (and clear) this register when rearming a channel with a changed IRQMASK setting. Failure to do so could generate an interrupt based on the stored interrupt flag. 13.2.6 DMA Configuration Data Structure For each DMA channel, the DMA configuration data structure consists of eight bytes. The configuration data structure is described in Table 43. 13.2.7 DMA USB Endianess (CC2511Fx) When a USB FIFO is accessed using word transfer DMA the endianess of the word read/written can be controlled by setting the ENDIAN.USBWLE and ENDIAN.USBRLE configuration bits in the ENDIAN register. See section 13.15 for details.
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DMA Trigger number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
DMA Trigger name NONE PREV T1_CH0 T1_CH1 T1_CH2 T2_OVFL T3_CH0 T3_CH1 T4_CH0 T4_CH1 ST IOC_0 IOC_1 URX0 UTX0 URX1 UTX1 FLASH RADIO ADC_CHALL ADC_CH0 ADC_CH1 ADC_CH2 ADC_CH3 ADC_CH4 ADC_CH5 ADC_CH6 I2SRX ADC_CH7 I2STX ENC_DW ENC_UP -
Functional unit
Description
DMA DMA Timer 1 Timer 1 Timer 1 Timer 2 Timer 3 Timer 3 Timer 4 Timer 4 Sleep Timer IO Controller IO Controller USART0 USART0 USART1 USART1 Flash controller Radio ADC ADC ADC ADC ADC ADC ADC ADC I2S ADC I2S AES AES -
No trigger, setting DMAREQ.DMAREQx bit starts transfer DMA channel is triggered by completion of previous channel Timer 1, compare, channel 0 Timer 1, compare, channel 1 Timer 1, compare, channel 2 Not in use. Timer 2, overflow Timer 3, compare, channel 0 Timer 3, compare, channel 1 Timer 4, compare, channel 0 Timer 4, compare, channel 1 Sleep Timer compare IO pin input transition IO pin input transition USART0 RX complete USART0 TX complete USART1 RX complete USART1 TX complete Flash data write complete RF packet byte received/transmit ADC end of a conversion in a sequence, sample ready ADC end of conversion channel 0 in sequence, sample ready ADC end of conversion channel 1 in sequence, sample ready ADC end of conversion channel 2 in sequence, sample ready ADC end of conversion channel 3 in sequence, sample ready ADC end of conversion channel 4 in sequence, sample ready ADC end of conversion channel 5 in sequence, sample ready ADC end of conversion channel 6 in sequence, sample ready I2S RX complete ADC end of conversion channel 7 in sequence, sample ready I2S TX complete AES encryption processor requests download input data AES encryption processor requests upload output data Not in use.
28 29 30 31
Table 42: DMA Trigger Sources
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Table 43: DMA Configuration Data Structure
Byte Offset 0 1 2 3 4 Bit 7:0 7:0 7:0 7:0 7:5 Field Name SRCADDR[15:8] SRCADDR[7:0] DESTADDR[15:8] DESTADDR[7:0] VLEN[2:0] Description The DMA channel source address, high The DMA channel source address, low The DMA channel destination address, high. Note that flash memory is not directly writeable. The DMA channel destination address, high. Note that flash memory is not directly writeable. Variable length transfer mode. In word mode, bits 12:0 of the first word is considered as the transfer length. 000/111 001 Use LEN for transfer count Transfer the number of bytes/words specified by first byte/word + 1 (up to a maximum specified by LEN). Thus transfer count excludes length byte/word Transfer the number of bytes/words specified by first byte/word (up to a maximum specified by LEN). Thus transfer count includes length byte/word. Transfer the number of bytes/words specified by first byte/word + 2 (up to a maximum specified by LEN). Transfer the number of bytes/words specified by first byte/word + 3 (up to a maximum specified by LEN). reserved reserved
010
011 100 101 110 4 4:0 LEN[12:8]
The DMA channel transfer count. Used as maximum allowable length when VLEN != 000/111. The DMA channel counts in words when in WORDSIZE mode, and otherwise in bytes.
5
7:0
LEN[7:0]
The DMA channel transfer count. Used as maximum allowable length when VLEN != 000/111. The DMA channel counts in words when in WORDSIZE mode, and otherwise in bytes.
6 6
7 6:5
WORDSIZE TMODE[1:0]
Selects whether each DMA transfer shall be 8-bit (0) or 16-bit (1). The DMA channel transfer mode: 00 : Single 01 : Block 10 : Repeated single 11 : Repeated block
6
4:0
TRIG[4:0]
Select DMA trigger to use 00000 : No trigger (writing to DMAREQ is only trigger) 00001 : The previous DMA channel finished 00010 - 11111 : Selects one of the triggers shown in Table 42. The trigger is selected in the order shown in the table.
7
7:6
SRCINC[1:0]
Source address increment mode (after each transfer): 00 : 0 bytes/words 01 : 1 bytes/words 10 : 2 bytes/words 11 : -1 bytes/words
7
5:4
DESTINC[1:0]
Destination address increment mode (after each transfer): 00 : 0 bytes/words 01 : 1 bytes/words 10 : 2 bytes/words 11 : -1 bytes/words
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Byte Offset 7 Bit 3 Field Name IRQMASK Description Interrupt Mask for this channel. 0 : Disable interrupt generation 1 : Enable interrupt generation upon DMA channel done 7 2 M8 Mode of 8 bit for VLEN transfer length; only applicable when WORDSIZE=0. 0 : Use all 8 bits for transfer count 1 : Use 7 LSB for transfer count 7 1:0 PRIORITY[1:0] The DMA channel priority: 00 : Low, CPU has priority. 01 : Guaranteed, DMA at least every second try. 10 : High, DMA has priority 11 : Reserved.
th
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13.2.8 DMA registers This section describes the SFR registers associated with the DMA Controller
DMAARM (0xD6) - DMA Channel Arm
Bit Name Reset R/W Description DMA abort. This bit is used to stop ongoing DMA transfers. Writing a 1 to this bit will abort all channels which are selected by setting the corresponding DMAARM bit to 1 0 : Normal operation 1 : Abort channels all selected channels
7
ABORT
0
R0/W
6:5 4
DMAARM4
00 0
R/W R/W
Not used DMA arm channel 4 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion.
3
DMAARM3
0
R/W
DMA arm channel 3 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion.
2
DMAARM2
0
R/W
DMA arm channel 2 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion.
1
DMAARM1
0
R/W
DMA arm channel 1 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion.
0
DMAARM0
0
R/W
DMA arm channel 0 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion.
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DMAREQ (0xD7) - DMA Channel Start Request and Status
Bit Name Reset R/W Description Not used DMA transfer request, channel 4 Manual trigger, set to 1 to start a transfer on the DMA channel (has the same effect as a single trigger event.). This bit is cleared when the DMA channel is granted access.
7:5 4
DMAREQ4
000 0
R0 R/W1 H0
3
DMAREQ3
0
R/W1 H0
DMA transfer request, channel 3 Manual trigger, set to 1 to start a transfer on the DMA channel (has the same effect as a single trigger event.). This bit is cleared when the DMA channel is granted access.
2
DMAREQ2
0
R/W1 H0
DMA transfer request, channel 2 Manual trigger, set to 1 to start a transfer on the DMA channel (has the same effect as a single trigger event.). This bit is cleared when the DMA channel is granted access.
1
DMAREQ1
0
R/W1 H0
DMA transfer request, channel 1 Manual trigger, set to 1 to start a transfer on the DMA channel (has the same effect as a single trigger event.). This bit is cleared when the DMA channel is granted access.
0
DMAREQ0
0
R/W1 H0
DMA transfer request, channel 0 Manual trigger, set to 1 to start a transfer on the DMA channel (has the same effect as a single trigger event.). This bit is cleared when the DMA channel is granted access.
DMA0CFGH (0xD5) - DMA Channel 0 Configuration Address High Byte
Bit Name Reset R/W Description The DMA channel 0 configuration address, high order
7:0
DMA0CFG[15:8]
0x00
R/W
DMA0CFGL (0xD4) - DMA Channel 0 Configuration Address Low Byte
Bit Name Reset R/W Description The DMA channel 0 configuration address, low order
7:0
DMA0CFG[7:0]
0x00
R/W
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DMA1CFGH (0xD3) - DMA Channel 1-4 Configuration Address High Byte
Bit Name Reset R/W Description The DMA channel 1-4 configuration address, high order
7:0
DMA1CFG[15:8]
0x00
R/W
DMA1CFGL (0xD2) - DMA Channel 1-4 Configuration Address Low Byte
Bit Name Reset R/W Description The DMA channel 1-4 configuration address, low order
7:0
DMA1CFG[7:0]
0x00
R/W
DMAIRQ (0xD1) - DMA Interrupt Flag
Bit Name Reset R/W Description Not used DMA channel 4 interrupt flag. 0 : DMA channel transfer not complete 1 : DMA channel transfer complete/interrupt pending
7:5 4
DMAIF4
000 0
R/W0 R/W0
3
DMAIF3
0
R/W0
DMA channel 3 interrupt flag. 0 : DMA channel transfer not complete 1 : DMA channel transfer complete/interrupt pending
2
DMAIF2
0
R/W0
DMA channel 2 interrupt flag. 0 : DMA channel transfer not complete 1 : DMA channel transfer complete/interrupt pending
1
DMAIF1
0
R/W0
DMA channel 1 interrupt flag. 0 : DMA channel transfer not complete 1 : DMA channel transfer complete/interrupt pending
0
DMAIF0
0
R/W0
DMA channel 0 interrupt flag. 0 : DMA channel transfer not complete 1 : DMA channel transfer complete/interrupt pending
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ENDIAN (0x95) - USB Endianess Control (CC2511Fx)
Bit 7:2 1 Name Reset 0 0 R/W R0 R/W Description Not used. Always 000000. USB Write Endianess setting for DMA channel word transfers to USB. 0 1 0 Big Endian Little Endian
USBWLE
USBRLE
0
R/W
USB Read Endianess setting for DMA channel word transfers from USB. 0 1 Big Endian Little Endian
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13.3 16-bit Timer, Timer 1 Timer 1 is an independent 16-bit timer which supports typical timer/counter functions such as input capture, output compare and PWM functions. The timer has three independent capture/compare channels. The timer uses one I/O pin per channel. The timer is used for a wide range of control and measurement applications and the availability of up/down count mode with three channels will for example allow implementation of motor control applications. The features of Timer 1 are as follows: * * * * * * * * * Three capture/compare channels Rising, falling, or any edge input capture Set, clear or toggle output compare Free-running, modulo counter operation or up/down is 24 MHz for CC2511Fx. When the 13 MHz RC oscillator is used as system clock source, then the highest clock frequency used by Timer 1 is 13 MHz. The counter operates as either a free-running counter, a modulo counter or as an up/down counter for use in centre-aligned PWM. It is possible to read the 16-bit counter value through the two 8-bit SFRs; T1CNTH and T1CNTL, containing the high-order byte and low-order byte respectively. When the T1CNTL is read, the high-order byte of the counter at that instant is buffered in T1CNTH so that the high-order byte can be read from T1CNTH. Thus T1CNTL shall always be read first before reading T1CNTH. All write accesses to the T1CNTL register will reset the 16-bit counter. The counter produces an interrupt request when the terminal count value (overflow) is reached. It is possible to clear and halt the counter with T1CTL control register settings. The counter is started when a value other than 00 is written to T1CTL.MODE. If 00 is written to T1CTL.MODE the counter halts at its present value. 13.3.2 Timer 1 Operation In general, the control register T1CTL is used to control the timer operation. The various modes of operation are described below. 13.3.3 Free-running Mode In the free-running mode of operation the counter starts from 0x0000 and increments at each active clock edge. When the counter reaches 0xFFFF the counter is loaded with 0x0000 and continues incrementing its value as shown in Figure 15. When the terminal count value 0xFFFF is reached, the flag T1CTL.OVFIF is set. An interrupt request is generated if the corresponding interrupt mask bit TIMIF.OVFIM is set. The free-running mode can be used to generate independent time intervals and output signal frequencies.
Clock prescaler for divide by 1, 8, 32 or 128 Interrupt request generated on each capture/compare and terminal count Capture triggered by radio DMA trigger function Delta-Sigma Modulator (DSM) mode
13.3.1 16-bit Timer Counter The timer consists of a 16-bit counter that increments or decrements at each active clock edge. The period of the active clock edges is defined by the register bits CLKCON.TICKSPD which sets the global division of the system clock giving a variable clock tick frequency from 0.203 MHz to 26 MHz for CC2510FX and 0.1875 MHz to 24 MHz for CC2511Fx. This is further divided in Timer 1 by the prescaler value set by T1CTL.DIV. This prescaler value can be from 1 to 128. Thus the lowest clock frequency used by Timer 1 is 1586.9 Hz and the highest is 26 MHz when the 26 MHz crystal oscillator is used as system clock source (CC2510FX). The lowest clock frequency used by Timer 1 is 1464.8 Hz and the highest
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FFFFh
0000h
overflow
overflow
Figure 15: Free-running mode 13.3.4 Modulo Mode When the timer operates in modulo mode the 16-bit counter starts at 0x0000 and increments at each active clock edge. When the counter reaches the terminal count value held in registers T1CC0H:T1CC0L, the counter is reset to 0x0000 and continues to increment. The flag T1CTL.OVFIF is set when the terminal count value (overflow) is reached. An interrupt request is generated if the corresponding interrupt mask bit TIMIF.OVFIM is set. The modulo mode can be used for applications where a count value other then 0xFFFF is required. The counter operation is shown in Figure 16.
T1CC0
0000h
overflow
overflow
Figure 16: Modulo mode 13.3.5 Up/down Mode In the up/down timer mode, the counter repeatedly starts from 0x0000 and counts up until the value held in T1CC0H:T1CC0L is reached and then the counter counts down until 0x0000 is reached as shown in Figure 17. This timer mode is used when symmetrical output pulses are required with a period other than 0xFFFF, and therefore allows implementation of centre-aligned PWM output applications. The flag T1CTL.OVFIF is set when the timer turns around at 0x0000. The counter is reset to 0x000 by writing any value to T1CNTL.
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Figure 17 : Up/down mode 13.3.6 Channel Mode Control The channel mode is set with each channel's control and status register T1CCTLn. The settings include input capture and output compare modes. 13.3.7 Input Capture Mode When a channel is configured as an input capture channel, the I/O pin associated with that channel, is configured as an input. After the timer has been started, a rising edge, falling edge or any edge on the input pin will trigger a capture of the 16-bit counter contents into the associated capture register. Thus the timer is able to capture the time when an external event takes place. Note: before an I/O pin can be used by the timer, the required I/O pin must be configured as a Timer 1 peripheral pin as described in section 13.1.4 on page 67 . The channel input pin is synchronized to the internal system clock. Thus pulses on the input pin must have a minimum duration greater than the system clock period. The content of the 16-bit capture register is read out from registers T1CCnH:T1CCnL. When the capture takes place the interrupt flag for the channel is set. This bit is T1CTL.CH0IF for channel 0, T1CTL.CH1IF for channel 1, and T1CTL.CH2IF for channel 2. An interrupt request is generated if the corresponding interrupt mask bit on T1CCTL0.IM, T1CCTL1.IM, or T1CCTL2.IM, respectively, is set. 13.3.7.1 RF Event Capture Each timer channel may be configured so that an RF interrupt RFIF event will trigger a capture instead of the normal input pin capture. This function is selected with the register bit T1CCTLx.CPSEL which selects to use either the input pin or the RFIF interrupt as capture event. When RFIF is selected as capture input, the interrupt source(s) enabled by RFIM (see section 15.3.1 on page 193) will trigger a capture. In this way the timer can be used to capture a value when e.g. a start of frame delimiter (SFD) is detected. 13.3.8 Output Compare Mode In output compare mode the I/O pin associated with a channel is set as an output. After the timer has been started, the contents of the counter is compared with the contents of the channel compare register T1CCnH:T1CCnL. If the compare register equals the counter contents, the output pin is set, reset or toggled according to the compare output mode setting of T1CCTLn.CMP. Note that all edges on output pins are glitch-free when operating in a given output compare mode. Writing to the compare register T1CCnL is buffered so that a value written to T1CCnL does not take effect until the corresponding high order register, T1CCnH is written. For output compare modes 1-3, a new value written to the compare register T1CCnH:T1CCnL takes effect after the registers have been written. For other output compare modes the new value written to the compare register take effect when the timer reaches 0x0000. Note that channel 0 has fewer output compare modes than channel 1 and 2 because T1CC0H:T1CC0L has a special function in modes 6 and 7, meaning these modes would not be useful for channel 0. When a compare occurs, the interrupt flag for the channel is set. This bit is T1CTL.CH0IF for channel 0, T1CTL.CH1IF for channel 1, and T1CTL.CH2IF for channel 2. An interrupt request is generated if the corresponding
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interrupt mask bit on T1CCTL0.IM, T1CCTL1.IM, or T1CCTL2.IM, respectively, is set. Examples of output compare modes in various timer modes are given in the following figures. Edge-aligned PWM output signals can be generated using the timer modulo mode and channels 1 and 2 in output compare mode 5 or 6 as shown in Figure 19. The period of the PWM signal is determined by the setting T1CC0 and the duty cycle for the channel output is determined by T1CCn. The timer freerunning mode may also be used. In this case CLKCON.TICKSPD and the prescaler divider value T1CTL.DIV set the period of the PWM signal. The polarity of the PWM signal is determined by whether output compare mode 5 or 6 is used. PWM output signals can also be generated using output compare modes 3 and 4 as shown in the same figure, or by using modulo mode as shown in Figure 19. Using output compare mode 3 and 4 is preferred for simple PWM. Centre-aligned PWM outputs can be generated when the timer up/down mode is selected. The channel output compare mode 3 or 4 is selected depending on required polarity of the PWM signal. The period of the PWM signal is determined by T1CC0 and the duty cycle for the channel output is determined by T1CCn. In some types of applications, a defined delay or dead time is required between outputs. Typically this is required for outputs driving an H-bridge configuration to avoid uncontrolled cross-conduction in one side of the H-bridge. The delay or dead-time can be obtained in the PWM outputs by using T1CCn as shown in the following: Assuming that channel 1 and channel 2 are used to drive the outputs using timer up/down mode and the channels use output compare modes 3 and 4 respectively. If T1CC1 is greater than T1CC2, then the timer period (in Timer 1 clock periods) is: TP = T1CC0 x 2 and the dead time, i.e. the time from when the channel 1 output goes low until the channel 2 output goes high, (in Timer 1 clock periods) is given by: TD = T1CC1 - T1CC2
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Figure 18: Output compare modes, timer free-running mode
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Figure 19: Output compare modes, timer modulo mode
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Figure 20: Output modes, timer up/down mode
13.3.9 Timer 1 Interrupts There is one interrupt vector assigned to the timer. An interrupt request is generated when one of the following timer events occur: * * * Counter reaches terminal count value or turns around on zero Input capture event. Output compare event The register bits T1CTL.OVFIF, T1CTL.CH0IF, T1CTL.CH1IF, and T1CTL.CH2IF contains the interrupt flags for the terminal count value event, and the three channel compare/capture events, respectively. An interrupt request is only generated when the corresponding interrupt mask bit is set. The interrupt mask bits are T1CCTL0.IM, T1CCTL1.IM, T1CCTL2.IM and
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TIMIF.OVFIM. If there are other pending interrupts, the corresponding interrupt flag must be cleared by software before a new interrupt request is generated. Also, enabling an interrupt mask bit will generate a new interrupt request if the corresponding interrupt flag is set. When the timer is used in Free-running Mode or Modulo Mode the interrupt flags are set as follows: * T1CTL.CH0IF, T1CTL.CH1IF and T1CTL.CH2IF are set on compare/capture event T1CTL.OVFIF is set when counter reaches terminal count value See Table 42 for a list of all DMA triggers.
13.3.11 DSM Mode Timer 1 also contains a 1-bit Delta Sigma Modulator (DSM) of second order that can be used to produce a high quality mono audio output PWM signal. The DSM removes the need for high order external filtering required when using regular PWM mode. The DSM operates at a fixed speed of either 1/4 or 1/8 of the Timer 1 update speed (CLKCON.TICKSPD) while input samples are updated at a configurable sampling rate set by Timer 1 channel 0. An interpolator is used to match the sampling rate with the DSM update rate. This interpolator is of first order with a scaling compensation. The scaling compensation is due to variable gain defined by the difference in sampling speed and DSM speed. This interpolation mechanism can be disabled, thus using a zeroth interpolator. In addition to the interpolator, a shaper can be used to account for differences in rise/fall times in the output signal. This shaper ensures a rising and a falling edge per bit and will thus limits the output swing to the range 1/8 to 7/8 of I/O VDD when the DSM operates at 1/8 of the Timer 1 update speed or 1/4 to 3/4 of I/O VDD when the DSM operates at 1/4 of the Timer 1 update speed. The DSM is used as in PWM mode where channel 0 defines the period/sampling rate. The DSM can not use the Timer 1 prescaler to further slow down the period. CLKCON.TICKSPD, however, can be used. Timer 1 channel 0 must be configured to compare modulo mode and have a terminal count value that matches the incoming sample rate. Table 44 shows some Timer 1 channel 0 periode settings (T1CC0 register) for different Timer 1 clock speeds and data rates (note that tick speed is not used, i.e. CLKCON.TICKSPD = 000).
*
When the timer is used in Up/Down Mode the interrupt flags are set as follows: In compare mode: * T1CTL.CH0IF and T1CTL.OVFIF are set when counter turns around on zero T1CTL.CH1IF and T1CTL.CH2IF are set on compare event T1CTL.CH0IF, T1CTL.CH1IF and T1CTL.CH2IF are set on capture event T1CTL.OVFIF is set when counter turns around on zero
*
In capture mode: *
*
13.3.10 Timer 1 DMA Triggers There are three DMA triggers associated with Timer 1, one for each channel. These are DMA triggers T1_CH0, T1_CH1 and T1_CH2 which are generated when the corresponding interrupt flags are set: * * * T1_CH0 is generated T1CTL.CH0IF is set T1_CH1 is generated T1CTL.CH0IF is set T1_CH2 is generated T1CTL.CH0IF is set when when when
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Data rate 8 kHz @ 24 MHz 8 kHz @ 26 MHz 16 kHz @ 24 MHz 16 kHz @ 26 MHz 48 kHz @ 24 MHz 48 kHz @ 26 MHz 64 kHz @ 24 MHz 64 kHz @ 26 MHz T1CC0H 0x0B 0x0C 0x05 0x06 0x01 0x02 0x01 0x01 T1CC0L 0xB7 0xB1 0xDB 0x59 0xF3 0x1D 0x76 0x96
Table 44 Channel 0 period setting for some sampling rates (CLKCON.TICKSPD = 000) The DSM starts immediately after DSM mode has been enabled by setting the T1CCTL1.CMP field. Thus, all configuration should have been performed prior to enabling DSM mode. Also, the Timer 1 counter should be cleared and started just before starting the DSM operation. A simple procedure for setting up DSM mode should then be as follows: 1. Suspend timer 1 (T1CTL.MODE = 0) 2. Clear timer counter by writing any value to T1CNTL, (T1CNT = 0x0000) 3. Set the sample rate by writing the Timer 1 channel 0 count period, T1CC0. 4. Set Timer 1 channel 0 compare mode (T1CCTL0.MODE = 1) 5. Load first sample if available (or zero if no sample available) into T1CC1H:T1CC1L. 6. Set timer operation to modulo mode (T1CTL.MODE = 2) 7. Configure the DSM by setting the MODE and CAP fields of the T1CCT1 register. 8. Enable DSM mode (T1CCTL1.CMP = 7) 13.3.12 Timer 1 Registers This section describes the Timer 1 registers that consist of the following registers: * * * * * * T1CNTH - Timer 1 Count High T1CNTL - Timer 1 Count Low T1CTL - Timer 1 Control and Status T1CCTLx - Timer 1 Capture/Compare Control Channel x x x On each Timer 1 IRQ or Timer 1 DMA trigger, write a new sample to the T1CC1H:T1CC1L registers. The least significant bits must be written to T1CC1L before the most significant bits are written to T1CC1H. The samples written must be signed 2's complement values. The 2 least significant bits will always be treated as 0, thus the effective sample size is 14 bits.
T1CCxH - Timer 1 Channel Capture/Compare Value High T1CCxL - Timer 1 Channel Capture/Compare Value Low
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T1CNTH (0xE3) - Timer 1 Counter High
Bit 7:0 Name Reset 0x00 R/W R Description Timer count high order byte. Contains the high byte of the 16-bit timer counter buffered at the time T1CNTL is read.
CNT[15:8]
T1CNTL (0xE2) - Timer 1 Counter Low
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer count low order byte. Contains the low byte of the 16-bit timer counter. Writing anything to this register results in the counter being cleared to 0x0000.
CNT[7:0]
T1CTL (0xE4) - Timer 1 Control and Status
Bit 7 6 5 4 Name Reset 0 0 0 0 R/W R/W0 R/W0 R/W0 R/W0 Description Timer 1 channel 2 interrupt flag. Set when the channel 2 interrupt condition occurs. Writing a 1 has no effect. Timer 1 channel 1 interrupt flag. Set when the channel 1 interrupt condition occurs. Writing a 1 has no effect. Timer 1 channel 0 interrupt flag. Set when the channel 0 interrupt condition occurs. Writing a 1 has no effect. Timer 1 counter overflow interrupt flag. Set when the counter reaches the terminal count value in free-running or modulo mode. Writing a 1 has no effect. Prescaler divider value. Generates the active clock edge used to update the counter as follows: 00 01 10 11 1:0 Tick frequency/1 Tick frequency/8 Tick frequency/32 Tick frequency/128
CH2IF CH1IF CH0IF OVFIF
3:2
DIV[1:0]
00
R/W
MODE[1:0]
00
R/W
Timer 1 mode select. The timer operating mode is selected as follows: 00 01 10 11 Operation is suspended Free-running, repeatedly count from 0x0000 to 0xFFFF Modulo, repeatedly count from 0x0000 to T1CC0 Up/down, repeatedly count from 0x0000 to T1CC0 and from T1CC0 down to 0x0000
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T1CCTL0 (0xE5) - Timer 1 Channel 0 Capture/Compare Control
Bit 7 Name Reset 0 R/W R/W Description Capture select. Timer 1 channel 0 captures on RFIF interrupt from RF transceiver or capture input pin. 0 1 6 5:3 Use normal capture input Use RFIF interrupt from RF transceiver for capture
CPSEL
IM CMP[2:0]
1 000
R/W R/W
Channel 0 interrupt mask. Enables interrupt request when set. Channel 0 compare mode select. Selects action on output when timer value equals compare value in T1CC0 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) Clear output on compare-up, set on 0 (set on comparedown in up/down mode) Not used Not used Not used
2
MODE
0
R/W
Mode. Select Timer 1 channel 0 capture or compare mode 0 1 Capture mode Compare mode
1:0
CAP[1:0]
00
R/W
Channel 0 capture mode select 00 01 10 11 No capture Capture on rising edge Capture on falling edge Capture on both edges
T1CC0H (0xDB) - Timer 1 Channel 0 Capture/Compare Value High
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer 1 channel 0 capture/compare value, high order byte
T1CC0[15:8]
T1CC0L (0xDA) - Timer 1 Channel 0 Capture/Compare Value Low
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer 1 channel 0 capture/compare value, low order byte
T1CC0[7:0]
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T1CCTL1 (0xE6) - Timer 1 Channel 1 Capture/Compare Control
Bit 7 Name Reset 0 R/W R/W Description Capture select. Timer 1 channel 1 captures on RFIF interrupt from RF transceiver or capture input pin 0 1 6 5:3 Use normal capture input Use RFIF interrupt from RF transceiver for capture
CPSEL
IM CMP[2:0]
1 000
R/W R/W
Channel 1 interrupt mask. Enables interrupt request when set. Channel 1 compare mode select. Selects action on output when timer value equals compare value in T1CC1 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) Clear output on compare-up, set on 0 (set on comparedown in up/down mode) Clear when equal T1CC0, set when equal T1CC1 Set when equal T1CC0, clear when equal T1CC1 DSM mode enable
2
MODE
0
R/W
Mode. Select Timer 1 channel 1 capture or compare mode. (timer mode) / Select DSM update speed (DSM mode) 0 1 Capture mode / DSM at timer/8 update speed Compare mode / DSM at timer/4 update speed
1:0
CAP[1:0]
00
R/W
Channel 1 capture mode select (timer mode) / DSM interpolator and output shaping configuration (DSM mode) 00 No capture / DSM interpolator and output shaping enabled 01 Capture on rising edge / DSM interpolator enabled and output shaping disabled 10 Capture on falling edge / DSM interpolator disabled and output shaping enabled 11 Capture on all edges / DSM interpolator and output shaping disabled
T1CC1H (0xDD) - Timer 1 Channel 1 Capture/Compare Value High
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer 1 channel 1 capture/compare value, high order byte (timer mode) DSM data high order byte (DSM mode)
T1CC1[15:8]
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T1CC1L (0xDC) - Timer 1 Channel 1 Capture/Compare Value Low
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer 1 channel 1 capture/compare value, low order byte (timer mode) DSM data low order byte. The two least significant bits are not used. (DSM mode)
T1CC1[7:0]
T1CCTL2 (0xE7) - Timer 1 Channel 2 Capture/Compare Control
Bit 7 Name Reset 0 R/W R/W Description Capture select. Timer 1 channel 2 captures on RFIF from RF transceiver or capture input pin 0 1 6 5:3 Use normal capture input Use RFIF from RF transceiver for capture
CPSEL
IM CMP[2:0]
1 000
R/W R/W
Channel 2 interrupt mask. Enables interrupt request when set. Channel 2 compare mode select. Selects action on output when timer value equals compare value in T1CC2 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) Clear output on compare-up, set on 0 (set on comparedown in up/down mode) Clear when equal T1CC0, set when equal T1CC2 Set when equal T1CC0, clear when equal T1CC2 Not used
2
MODE
0
R/W
Mode. Select Timer 1 channel 2 capture or compare mode 0 1 Capture mode Compare mode
1:0
CAP[1:0]
00
R/W
Channel 2 capture mode select 00 01 10 11 No capture Capture on rising edge Capture on falling edge Capture on all edges
T1CC2H (0xDF) - Timer 1 Channel 2 Capture/Compare Value High
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer 1 channel 2 capture/compare value, high order byte
T1CC2[15:8]
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T1CC2L (0xDE) - Timer 1 Channel 2 Capture/Compare Value Low
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer 1 channel 2 capture/compare value, low order byte
T1CC2[7:0]
The TIMIF.OVFIM register bit resides in the TIMIF register, which is described together with timer 3 and timer 4
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13.4 MAC Timer (Timer 2) The MAC timer is designed for slot timing operations for MAC layers of RF protocols. The timer includes a highly tunable prescaler allowing the user to select a timer tick interval that equals, or is an integer fraction of a transmission slot. * * 8-bit timer 18-bit tunable prescaler The timer tick period T, is given as: T = T2PR * Val(T2CTL.TIP) clock cycles. where the function Val(x) is set by the tick period, T2CTL.TIP and defined as Val(00)=64 Val(01)=128 Val(10)=256 Val(11)=1024 The tick generator can be set to run freely or to run only when the timer holds a nonzero value. Whenever the tick generator is started it starts from its zero state. At this point there will be T2PR*Val(T2CTL.TIP)-1 clock cycles until the next tick. 13.4.2 Timer 2 Registers The SFR registers associated with Timer 2 are listed in this section. These registers are the following: * * * T2CTL - Timer 2 Control T2PRE - Timer 2 Prescaler T2CT - Timer 2 Count
13.4.1 Timer Operation This section describes the operation of the timer. The timer count can be read from the T2CT SFR register. The timer decrements by 1 at each timer tick. When the timer count reaches 0x00 the timer expires and does not wrap around. When the timer expires, the register bit T2CTL.TEX is set to 1. An interrupt request is generated when the timer expires, if the interrupt mask T2CTL.INT is 1. When a new value is written to the timer count register, T2CT, then this value is stored in the counter immediately. If a tick and a write to T2CT occurs at the same time, the written value will be decremented before it is stored.
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T2CTL (0x9E) - Timer 2 Control
Bit 7 6 5 4 Name Reset 0 0 0 0 R/W R/W0 R/W0 R/W R/W Description Not used. Timer expired. This bit is set when the timer expires. Writing a 1 to this bit has no effect Reserved. Should always be written as 0 Interrupt enable. Select interrupt generated on timer expiration 0 Interrupt disabled 1 Interrupt enabled 3 2
TEX INT
TIG
0 0
R/W R/W
Reserved. Should always be written as 0 Tick generator mode. 0 Tick generator is running when T2CT not equal to 00h. The tick generator will always start running form its null state. 1 Tick generator is in free-running mode. If it is not already running it will start from its null state when a `1' is written to TIG.
1:0
TIP[1:0]
00
R/W
Tick period. Selects tick period based on prescaler multiplier value. 00 Tick period is T2PR * 64 clock cycles 01 Tick period is T2PR * 128 clock cycles 10 Tick period is T2PR * 256 clock cycles 11 Tick period is T2PR * 1024 clock cycles
T2CT (0x9C) - Timer 2 Count
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer count. Contents of 8-bit counter
CNT[7:0]
T2PR (0x9D) - Timer 2 Prescaler
Bit Name Reset R/W Description
7:0
PR[7:0]
0x00
R/W
Timer prescaler multiplier. 0x00 is interpreted as 256
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13.5 Sleep Timer The Sleep Timer is used to control when the CC2510FX/CC2511Fx exits from the lowpower modes PM1 or PM2. Thus the Sleep Timer can be used to implement a wake up functionality which enables CC2510FX/CC2511Fx to periodically wake up from low-power mode and listen for incoming RF packets. Additionally the Sleep Timer can be used as a real time clock when the 32.768 kHz crystal oscillator is used. 13.5.1 Sleep Timer Operation This section describes the operation of the timer. The Sleep Timer consists of a 31-bit counter. The appropriate bits of this counter are selected according to a resolution setting determined by the WORCTL.WOR_RES register bits. The Sleep Timer is either clocked by the 32.768 kHz crystal oscillator or the 34.6667 kHz (26MHz / 750) low power RC oscillator. The timer runs in all power modes except PM3 where all oscillators are powered off. The timer can be reset by writing 1 to the WORCTL.WOR_RESET register bit. The Sleep Timer has a programmable timing event called Event 0. While in power mode PM1 or PM2, reaching Event 0 will turn on the digital voltage regulator and start the crystal oscillator. The time between two consecutive Event 0's is programmed with timeout value set by a mantissa value given by WOREVT1.EVENT0 and WOREVT0.EVENT0, and an exponent value set by WORCTRL.WOR_RES. The equation is: 13.5.2 Low power RC oscillator and timing This section applies to using the low power RC oscillator as clock source for the Sleep Timer. The frequency of the low-power RC oscillator, which can be used as clock source for the Sleep Timer, varies with temperature and supply voltage. In order to keep the frequency as accurate as possible, the RC oscillator will be calibrated whenever possible, which is when the 26/48 MHz crystal oscillator is running and the chip is in the PM0 power mode. When the chip goes to PM1 or PM2, the RC oscillator will use the last valid calibration result. The frequency of the low power RC oscillator is therefore locked to the 26/48 MHz crystal oscillator frequency divided by 750. To generate a 32.768 kHz RC oscillator frequency, use a 24.576 MHz crystal for the 26 MHz crystal oscillator. 13.5.3 Sleep Timer Interrupt The Sleep Timer generates the Sleep Timer interrupt, ST, when the timing event Event 0 occurs. This interrupt source can be masked using the WORIRQ.EVENT0_MASK interrupt mask bit. The interrupt flag bit WORIRQ.EVENT0_FLAG will be set when Event 0 occurs. 13.5.4 Sleep Timer Registers The SFR registers associated with the Sleep Timer are described in the following
t Event 0 =
750 EVENT 0 2 5WOR _ RES f XOSC
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WORTIME0 (0xA5) - Sleep Timer Low Byte
Bit 7:0 Name Reset 0x00 R/W R Description Timer 16-bit value, low byte. The 16 bits are selected from the 31bit Sleep Timer according to the setting of
WORTIME0[7:0]
WORCTL.WOR_RES[1:0]
WORTIME1 (0xA6) - Sleep Timer High Byte
Bit 7:0 Name Reset 0x00 R/W R Description Timer 16-bit value, high byte. The 16 bits are selected from the 31-bit Sleep Timer according to the setting of
WORTIME1[15:8]
WORCTL.WOR_RES[1:0]
WOREVT1 (0xA4) - Sleep Timer Event0 Timeout High
Bit Name Reset 0x87 R/W R/W Description High byte of Event 0 timeout register
7:0
EVENT0[15:8]
t Event 0 =
750 EVENT 0 2 5WOR _ RES f XOSC
WOREVT0 (0xA3) - Sleep Timer Event0 Timeout Low
Bit Name Reset 107 (0x6B) R/W R/W Description Low byte of Event 0 timeout register. The default Event 0 value gives 1.0s timeout, assuming a 26.0 MHz crystal.
7:0
EVENT0[7:0]
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WORCTL (0xA2) - Sleep Timer Control
Bit 7 6:4 3 2 1:0 Name Reset 0 111 0 00 R/W R0 R/W R0 R0/W1 R/W Description Not used Not used. Always write 111. Not used Reset timer. If a 1 is written to this bit location, the timer is reset. Writing 0 will have no effect. Always read as 0 Timer resolution Controls the resolution and maximum timeout of the WOR timer. Adjusting the resolution does not affect the clock cycle counter: 00 01 10 11 31.25 us resolution, 2 s max timeout (15:0) 1 ms resolution, 65 s max timeout (20:5) 32 ms resolution, 35 min max timeout (25:10) 1 s resolution, 18 h max timeout (30:15)
WOR_RESET
WOR_RES[1:0]
WORIRQ (0xA1) - Sleep Timer Interrupt Control
Bit Name Reset 00 0 0 R/W R0 R/W R/W Description Not used Not used. This bit must always be written as 0. Event 0 interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled
7:6 5 4
EVENT0_MASK
3:2 1 0
EVENT0_FLAG
00 0 0
R0 R/W0 R/W0
Not used Not used. This bit must always be written as 0. Event 0 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending
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13.6 8-bit Timer 3 and Timer 4 Timer 3 and 4 are 8-bit timers which support typical input capture and output compare operations using two capture/compare channels each. The timer allows generalpurpose timer and waveform generation functions. Features of Timer 3/4 are as follows: * * * * * * * Dual channel operation Rising, falling or any edge input compare Set, clear or toggle output compare Free-running, modulo or up/down counter operation Clock prescaler for divide by 1, 2, 4, 8, 16, 32, 64, 128 Interrupt request generated on each capture/compare and terminal count event DMA trigger function It is possible to read the 8-bit counter value through the SFR TxCNT where x refers to the timer number, 3 or 4. The possibility to clear and halt the counter is given with TxCTL control register settings. The counter is started when a 1 is written to TxCTL.START. If a 0 is written to TxCTL.START the counter halts at its present value. 13.6.2 Timer 3/4 Mode Control In general the control register TxCTL is used to control the timer operation. The timer modes are described in the following sections. 13.6.2.1 Free-running Mode In the free-running mode of operation the counter starts from 0x00 and increments at each active clock edge. When the counter reaches 0xFF the counter is loaded with 0x00 and continues incrementing its value. When the terminal count value 0xFF is reached (i.e. an overflow occurs), the interrupt flag TIMIF.TxOVFIF is set. If the corresponding interrupt mask bit TxCTL.OVFIM is set, an interrupt request is generated. The freerunning mode can be used to generate independent time intervals and output signal frequencies.
13.6.1 8-bit Timer Counter All timer functions are based on the main 8-bit counter found in Timer 3/4. The counter increments or decrements at each active clock edge. The period of the active clock edges is defined by the register bits CLKCON.TICKSPD which is further divided by the prescaler value set by TxCTL.DIV (where x refers to the timer number, 3 or 4). The counter operates as either a free-running counter, a down counter, a modulo counter or as an up/down counter.
Figure 21 Free-running Mode 13.6.2.2 Down mode In the down mode, after the timer has been started, the counter is loaded with the contents in TxCC. The counter then counts down to 0x00 and remains at 0x00. The flag TIMIF.TxOVFIF is set when 0x00 is reached. If the corresponding interrupt mask bit TxCTL.OVFIM is set, an interrupt request is generated. The timer down mode can generally be used in applications where an event timeout interval is required.
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Figure 22 Down Mode 13.6.2.3 Modulo Mode When the timer operates in modulo mode the 8-bit counter starts at 0x00 and increments at each active clock edge. When the counter reaches the value held in register TxCC the counter is reset to 0x00 and continues to increment. The flag TIMIF.TxOVFIF is set on this event. If the corresponding interrupt mask bit TxCTL.OVFIM is set, an interrupt request is generated. The modulo mode can be used for applications where a period other than 0xFF is required.
Figure 23 Modulo Mode
13.6.2.4 Up/down Mode In the up/down timer mode, the counter repeatedly starts from 0x00 and counts up until the value held in TxCC is reached and then the counter counts down until 0x00 is reached. This timer mode is used when symmetrical output pulses are required with a period other than 0xFF, and therefore allows implementation of centre-aligned PWM output applications. The counter is reset to 0x00 by writing to TxCTL.CLR.
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Figure 24 Up/down Mode 13.6.3 Channel Mode Control The channel modes for each channel are set by the control and status registers TxCCTLn, where n is the channel number, 0 or 1. The settings include input capture and output compare modes. 13.6.4 Input Capture Mode When the channel is configured as an input capture channel, the I/O pin associated with that channel is configured as an input. After the timer has been started, either a rising edge, a falling edge or any edge on the input pin triggers a capture of the 8-bit counter contents into the associated capture register. Thus the timer is able to capture the time when an external event takes place. The channel input pins are synchronized to the internal system clock. Thus pulses on the input pins must have a minimum duration greater than the system clock period. Note: before an input/output pin can be used by the timer, the required I/O pin must be configured as a Timer 3/4 peripheral pin as described in sections 13.1.4.4 and 13.1.4.5. The contents of the 8-bit capture registers, is read out from registers TxCCn. When a capture takes place the interrupt flag corresponding to the actual channel is set. This interrupt flag is TIMIF.TxCHnIF. An interrupt request is generated if the corresponding interrupt mask bit TxCCTLn.IM is set. 13.6.5 Output Compare Mode In output compare mode the I/O pin associated with a channel should be configured as an output. After the timer has been started, the contents of the counter is compared with the contents of the channel compare register TxCCn. If the compare register equals the counter contents, the output pin is set, reset or toggled according to the compare output mode setting of TxCCTL.CMP1:0. Note that all edges on output pins are glitch-free when operating in a given compare output mode. For simple PWM use, output compare modes 3 and 4 are preferred. Writing to the compare register TxCC0 does not take effect on the output compare value until the counter value is 0x00. Writing to the compare register TxCC1 takes effect immediately. When a compare occurs the interrupt flag corresponding to the actual channel is set. This interrupt flag is TIMIF.TxCHnIF. An interrupt request is generated if the corresponding interrupt mask bit TxCCTLn.IM is set. 13.6.6 Timer 3 and 4 interrupts There is one interrupt vector assigned to each of the timers. These are T3IF (interrupt 11) and T4IF (interrupt 12). An interrupt request is generated when one of the following timer events occur: * * * Counter reaches terminal count value. Input capture event. Output compare event
The SFR register TIMIF contains all interrupt flags for Timer 3 and Timer 4. The register bits TIMIF.TxOVFIF and TIMIF.TxCHnIF contain the interrupt flags for the two terminal count value events and the four channel compare/capture events, respectively. An interrupt request is only generated when the corresponding interrupt mask bit is set. If there are other pending interrupts, the
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corresponding interrupt flag must be cleared by the CPU before a new interrupt request can be generated. Also, enabling an interrupt mask bit will generate a new interrupt request if the corresponding interrupt flag is set. When the timer is used in Free-running Mode or Modulo Mode the interrupt flags are set as follows: * TIMIF.TxCH0IF TIMIF.TxCH1IF are compare/capture event set and on * TIMIF.TxOVFIF is set when the counter turns around on zero
13.6.7 Timer 3 and Timer 4 DMA triggers There are two DMA triggers associated with Timer 3 and two DMA triggers associated with Timer 4. These are DMA triggers T3_CH0, T3_CH1, T4_CH0 and T4_CH1 which are generated when the corresponding interrupt flags are set: * * * * T3_CH0 is generated TIMIF.T3CH0IF is set T3_CH1 is generated TIMIF.T3CH1IF is set T4_CH0 is generated TIMIF.T4CH0IF is set T4_CH1 is generated TIMIF.T4CH1IF is set when when when when
*
TIMIF.TxOVFIF is set when counter reaches terminal count value
When the timer is used in Up/Down Mode the interrupt flags are set as follows: In compare mode: * TIMIF.TxCH0IF and TIMIF.TxOVFIF are set when the counter turns around on zero TIMIF.TxCH1IF is set on compare event TIMIF.TxCH0IF and TIMIF.TxCH1IF are set on capture event
*
Refer to section 13.2 on page 84, for a description on use of DMA channels. 13.6.8 Timer 3 and 4 registers The Timer 3 and 4 registers are described on the following pages.
In capture mode: *
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T3CNT (0xCA) - Timer 3 Counter
Bit 7:0 Name Reset 0x00 R/W R Description Timer count byte. Contains the current value of the 8-bit counter.
CNT[7:0]
T3CTL (0xCB) - Timer 3 Control
Bit 7:5 Name Reset 000 R/W R/W Description Prescaler divider value. Generates the active clock edge used to clock the timer from CLKCON.TICKSPD as follows: 000 001 010 011 100 101 110 111 4 3 Tick frequency /1 Tick frequency /2 Tick frequency /4 Tick frequency /8 Tick frequency /16 Tick frequency /32 Tick frequency /64 Tick frequency /128
DIV[2:0]
START OVFIM
0 1
R/W R/W0
Start timer. Normal operation when set, suspended when cleared Overflow interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled
2 1:0
CLR MODE[1:0]
0 00
R0/W1 R/W
Clear counter. Writing high resets counter to 0x00 Timer 3 mode. Select the mode as follows: 00 01 10 11 Free running, repeatedly count from 0x00 to 0xFF Down, count from T3CC0 to 0x00 Modulo, repeatedly count from 0x00 to T3CC0 Up/down, repeatedly count from 0x00 to T3CC0 and down to 0x00
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T3CCTL0 (0xCC) - Timer 3 Channel 0 Capture/Compare Control
Bit 7 6 Name Reset 0 1 R/W R0 R/W Description Unused Channel 0 interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled 5:3
IM
CMP[2:0]
000
R/W
Channel 0 compare output mode select. Specified action on output when timer value equals compare value in T3CC0 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) Clear output on compare-up, set on 0 (set on comparedown in up/down mode) Set output on compare, clear on 0xFF Clear output on compare, set on 0x00 Not used
2
MODE
0
R/W
Mode. Select Timer 3 channel 0 capture or compare mode 0 1 Capture mode Compare mode
1:0
CAP[1:0]
00
R/W
Channel 0 capture mode select 00 01 10 11 No capture Capture on rising edge Capture on falling edge Capture on all edges
T3CC0 (0xCD) - Timer 3 Channel 0 Capture/Compare Value
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer capture/compare value channel 0
VAL[7:0]
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T3CCTL1 (0xCE) - Timer 3 Channel 1 Capture/Compare Control
Bit 7 6 Name Reset 0 1 R/W R0 R/W Description Unused Channel 1 interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled 5:3
IM
CMP[2:0]
000
R/W
Channel 1 compare output mode select. Specified action on output when timer value equals compare value in T3CC1 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) Clear output on compare-up, set on 0 (set on comparedown in up/down mode) Set output on compare, clear on T3CC0 Clear output on compare, set on T3CC0 Not used
2
MODE
0
R/W
Mode. Select Timer 3 channel 1 capture or compare mode 0 1 Capture mode Compare mode
1:0
CAP[1:0]
00
R/W
Channel 1 capture mode select 00 01 10 11 No capture Capture on rising edge Capture on falling edge Capture on all edges
T3CC1 (0xCF) - Timer 3 Channel 1 Capture/Compare Value
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer capture/compare value channel 1
VAL[7:0]
T4CNT (0xEA) - Timer 4 Counter
Bit 7:0 Name Reset 0x00 R/W R Description Timer count byte. Contains the current value of the 8-bit counter.
CNT[7:0]
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T4CTL (0xEB) - Timer 4 Control
Bit 7:5 Name Reset 00 R/W R/W Description Prescaler divider value. Generates the active clock edge used to clock the timer from CLKCON.TICKSPD as follows: 000 001 010 011 100 101 110 111 4 3 2 1:0 Tick frequency /1 Tick frequency /2 Tick frequency /4 Tick frequency /8 Tick frequency /16 Tick frequency /32 Tick frequency /64 Tick frequency /128
DIV[2:0]
START OVFIM CLR MODE[1:0]
0 1 0 00
R/W R/W0 R0/W1 R/W
Start timer. Normal operation when set, suspended when cleared Overflow interrupt mask Clear counter. Writing high resets counter to 0x00 Timer 4 mode. Select the mode as follows: 00 01 10 11 Free running, repeatedly count from 0x00 to 0x00 Down, count from T4CC0 to 0x00 Modulo, repeatedly count from 0x00 to T4CC0 Up/down, repeatedly count from 0x00 to T4CC0 and down to 0x00
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T4CCTL0 (0xEC) - Timer 4 Channel 0 Capture/Compare Control
Bit 7 6 5:3 Name Reset 0 1 000 R/W R0 R/W R/W Description Unused Channel 0 interrupt mask Channel 0 compare output mode select. Specified action on output when timer value equals compare value in T4CC0 000 001 010 011 100 101 110 111 2 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) Clear output on compare-up, set on 0 (set on comparedown in up/down mode) Set output on compare, clear on 0x00 Clear output on compare, set on 0x00 Not used
IM CMP[2:0]
MODE
0
R/W
Mode. Select Timer 4 channel 0 capture or compare mode 0 1 Capture mode Compare mode
1:0
CAP[1:0]
00
R/W
Channel 0 capture mode select 00 01 10 11 No capture Capture on rising edge Capture on falling edge Capture on all edges
T4CC0 (0xED) - Timer 4 Channel 0 Capture/Compare Value
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer capture/compare value channel 0
VAL[7:0]
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T4CCTL1 (0xEE) - Timer 4 Channel 1 Capture/Compare Control
Bit 7 6 5:3 Name Reset 0 1 000 R/W R0 R/W R/W Description Unused Channel 1 interrupt mask Channel 1 compare output mode select. Specified action on output when timer value equals compare value in T4CC1 000 001 010 011 100 101 110 111 2 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) Clear output on compare-up, set on 0 (set on comparedown in up/down mode) Set output on compare, clear on T4CC0 Clear output on compare, set on T4CC0 Not used
IM CMP[2:0]
MODE
0
R/W
Mode. Select Timer 4 channel 1 capture or compare mode 0 1 Capture mode Compare mode
1:0
CAP[1:0]
00
R/W
Channel 1 capture mode select 00 01 10 11 No capture Capture on rising edge Capture on falling edge Capture on all edges
T4CC1 (0xEF) - Timer 4 Channel 1 Capture/Compare Value
Bit 7:0 Name Reset 0x00 R/W R/W Description Timer capture/compare value channel 1
VAL[7:0]
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TIMIF (0xD8) - Timers 1/3/4 Interrupt Mask/Flag
Bit 7 6 5 Name Reset 0 1 0 R/W R0 R/W R/W0 Description Unused Timer 1 overflow interrupt mask Timer 4 channel 1 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending Writing a 1 has no effect. 4
OVFIM T4CH1IF
T4CH0IF
0
R/W0
Timer 4 channel 0 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending Writing a 1 has no effect.
3
T4OVFIF
0
R/W0
Timer 4 overflow interrupt flag 0 : no interrupt is pending 1 : interrupt is pending Writing a 1 has no effect.
2
T3CH1IF
0
R/W0
Timer 3 channel 1 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending Writing a 1 has no effect.
1
T3CH0IF
0
R/W0
Timer 3 channel 0 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending Writing a 1 has no effect.
0
T3OVFIF
0
R/W0
Timer 3 overflow interrupt flag 0 : no interrupt is pending 1 : interrupt is pending Writing a 1 has no effect.
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13.7 ADC 13.7.1 ADC Introduction The ADC supports up to 14-bit analog-todigital conversion. The ADC includes an analog multiplexer with up to eight individually configurable channels, reference voltage generator and conversion results written to memory through DMA. Several modes of operation are available. The main features of the ADC are as follows: * Selectable decimation rates which also sets the resolution (8 to 14 bits). * * Eight individual input channels, singleended or differential Reference voltage selectable as internal, external single ended, external differential or AVDD. Interrupt request generation DMA triggers at end of conversions Temperature sensor input Battery measurement capability
* * * *
AIN0 AIN7 VDD/3
TMP_SENSOR
...
input mux
Sigma-delta modulator
Decimation filter
Int 1.25V AIN7 AVDD AIN6-AIN7 ref mux
Clock generation and control
Figure 25: ADC block diagram.
13.7.2 ADC Operation This section describes the general setup and operation of the ADC and describes the usage of the ADC control and status registers accessed by the CPU. 13.7.2.1 ADC Core The ADC includes an ADC capable of converting an analog input into a digital representation with up to 14 bits resolution. The ADC uses a selectable positive reference voltage.
13.7.2.2 ADC Inputs The signals on the P0 port pins can be used as ADC inputs. In the following these port pint will be referred to as the AIN0AIN7 pins. The input pins AIN0-AIN7 are connected to the ADC. The ADC can be set up to automatically perform a sequence of conversions and optionally perform an extra conversion from any channel when the sequence is completed. It is possible to configure the inputs as single-ended or differential inputs. In the case where differential inputs are selected,
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the differential inputs consist of the input pairs AIN0-1, AIN2-3, AIN4-5 and AIN6-7. In addition to the input pins AIN0-AIN7, the output of an on-chip temperature sensor can be selected as an input to the ADC for temperature measurements. It is also possible to select a voltage corresponding to AVDD/3 as an ADC input. This input allows the implementation of e.g. a battery monitor in applications where this feature is required. 13.7.2.3 ADC conversion sequences The ADC will perform a sequence of conversions, and move the results to memory (through DMA) without any interaction from the CPU. The ADCCON2.SCH register bits are used to define an ADC conversion sequence, from the ADC inputs. A conversion sequence will contain a conversion from each channel from 0 up to and including the channel number programmed in ADCCON2.SCH when ADCCON2.SCH is set to a value less than 8. The single-ended inputs AIN0 to AIN7 are represented by channel numbers 0 to 7 in ADCCON2.SCH. Channel numbers 8 to 11 represent the differential inputs consisting of AIN0-AIN1, AIN2-AIN3, AIN4-AIN5 and AIN6-AIN7. Channel numbers 12 to 15 represent GND, internal voltage reference, temperature sensor and AVDD/3, respectively. When ADCCON2.SCH is set to a value between 8 and 12, the sequence will start at channel 8. For even higher settings, only single conversions are performed. In addition to this sequence of conversions, the ADC can be programmed to perform a single conversion from any channel as soon as the sequence has completed. This is called an extra conversion and is controlled with the ADCCON3 register. The conversion sequence can also be influenced with the ADCCFG register (see section 13.1.5 on page 69). The eight analog inputs to the ADC come from I/O pins, which are not necessarily programmed to be analog inputs. If a channel should normally be part of a sequence, but the corresponding analog input is disabled in the ADCCFG, then that channel will be skipped. For channels 8 to 12, both input pins must be enabled. 13.7.2.4 ADC Operating Modes This section describes the operating modes and initialization of conversions. The ADC has three control registers: ADCCON1, ADCCON2 and ADCCON3. These registers are used to configure the ADC and to report status. The ADCCON1.EOC bit is a status bit that is set high when a conversion ends and cleared when ADCH is read. The ADCCON1.ST bit is used to start a sequence of conversions. A sequence will start when this bit is set high, ADCCON1.STSEL="11" and no conversion is currently running. When the sequence is completed, this bit is automatically cleared. The ADCCON1.STSEL bits select which event that will start a new sequence of conversions. The options which can be selected are rising edge on external pin P2_0, end of previous sequence, a Timer 1 channel 0 compare event or ADCCON1.ST='1'. The ADCCON2 register controls how the sequence of conversions is performed. ADCCON2.SREF is used to select the reference voltage. The reference voltage should only be changed when no conversion is running. The ADCCON2.SDIV bits select the decimation rate (and thereby also the resolution and time required to complete a conversion and sample rate). The decimation rate should only be changed when no conversion is running. The last channel of a sequence is selected with the ADCCON2.SCH bits. The ADCCON3 register controls the channel number, reference voltage and decimation rate for the extra conversion. The extra conversion will take place immediately after the ADCCON3 register is updated. The coding of the register bits is exactly as for ADCCON2.
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13.7.2.5 ADC Conversion Results The digital conversion result is represented in two's complement form. For 14-bit resolution, the digital conversion result is 8191 when the analogue input is equal to the VREF, and the conversion result is -8192 when the analogue input is equal to -VREF, where VREF is the selected positive voltage reference. When single-ended input is used, only positive conversion results are generated effectively reducing the resolution to maximum 13 bits. The digital conversion result is available when ADCCON1.EOC is set to 1, in ADCH and ADCL. When reading the ADCCON2.SCH field, the number returned will indicate the last channel converted. Notice that when the value written to ADCCON2.SCH is less than 12, the number returned will be the number of the last channel converted + 1. 13.7.2.6 ADC Reference Voltage The positive reference voltage for analogue-to-digital conversions is selectable as either an internally generated 1.25V voltage, the AVDD pin, the external voltage applied to the AIN7 input pin or the differential voltage applied to the AIN6-AIN7 inputs. It is possible to select the reference voltage as the input to the ADC in order to perform a conversion of the reference voltage e.g. for calibration purposes. Similarly, it is possible to select the ground terminal GND as an input. 13.7.2.7 ADC Conversion Timing The 26/48 MHz crystal oscillator should be selected when the ADC is used. The ADC runs on a clock which is the 26/48 MHz system clock source divided by 6 to give a 4.33/4 MHz ADC clock. The delta sigma modulator and decimation filter both use the ADC clock for their calculations. The time required to perform a conversion depends on the selected decimation rate. When the decimation rate is set to for instance 128, the decimation filter uses exactly 128 of the ADC clock periods to calculate the result. When a conversion is started, the input multiplexer is allowed 16 ADC clock cycles to settle in case the channel has been changed since the previous conversion. The 16 clock cycles settling time applies to all decimation rates. Thus in general, the conversion time is given by: Tconv = (decimation rate + 16) x T where T = 0.23 s for CC2510FX T = 0.25 s for CC2511Fx
13.7.2.8 ADC Interrupts The ADC will generate an interrupt when an extra conversion has completed. An interrupt is not generated when a conversion from the sequence is completed. 13.7.2.9 ADC DMA Triggers The ADC will generate a DMA trigger every time a conversion from the sequence has completed. When an extra conversion completes, no DMA trigger is generated. There is one DMA trigger for each of the eight channels defined by the first eight possible settings for ADCCON2.SCH . The DMA trigger is active when a new sample is ready from the conversion for the channel. The DMA triggers are named ADC_CHx in Table 42 on page 90. In addition there is one DMA trigger, ADC_CHALL, which is active when new data is ready from any of the channels in the ADC conversion sequence.
13.7.2.10 ADC Registers This section describes the ADC registers.
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ADCL (0xBA) - ADC Data Low
Bit 7:2 1:0 Name Reset 0x00 00 R/W R R0 Description Least significant part of ADC conversion result. Not used. Always read as 0
ADC[5:0]
-
ADCH (0xBB) - ADC Data High
Bit 7:0 Name Reset 0x00 R/W R Description Most significant part of ADC conversion result.
ADC[13:6]
ADCCON1 (0xB4) - ADC Control 1
Bit 7 Name Reset 0 R/W R H0 Description End of conversion Cleared when both ADCH and ADCL has been read. If a new conversion is completed before the previous data has been read, the EOC bit will remain high. 0 1 6 conversion not complete conversion completed
EOC
ST
0
R/W1
Start conversion. Read as 1 until conversion has completed 0 1 no conversion in progress start a conversion sequence if ADCCON1.STSEL = "11" and no sequence is running.
5:4
STSEL[1:0]
11
R/W
Start select. Selects which event that will start a new conversion sequence. 00 01 10 11 External trigger on P2_0 pin. Full speed. Do not wait for triggers. Timer1 channel1 output = 1 ADCCON1.ST = 1
3:2
RCTRL[1:0]
00
R/W
Controls the 16 bit random generator. When written "01", the setting will automatically return to "00" when operation has completed. 00 01 10 11 Idle or operation completed. Clock the LFSR once (no unrolling). Reserved. Stopped. Random generator is turned off.
1:0
-
11
R/W
Reserved. Set to 11.
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ADCCON2 (0xB5) - ADC Control 2
Bit 7:6 Name Reset 00 R/W R/W Description Selects reference voltage used for the sequence of conversions 00 01 10 11 5:4 Internal 1.25V reference External reference on AIN7 pin AVDD pin External reference on AIN6-AIN7 differential input
SREF[1:0]
SDIV[1:0]
01
R/W
Sets the decimation rate for channels included in the sequence of conversions. The decimation rate also determines the resolution and time required to complete a conversion. 00 01 10 11 64 dec rate (8 bits resolution) 128 dec rate (10 bits resolution) 256 dec rate (12 bits resolution) 512 dec rate (14 bits resolution)
3:0
SCH[3:0]
00
R/W
Sequence Channel Select. Selects the end of the sequence. A sequence can either be from AIN0 to AIN7 (SCH<=7) or from the differential input AIN0-AIN1 to AIN6-AIN7 (8<=SCH<=11). For other settings, only single conversions are performed. When read, these bits will indicate the channel number of current conversion result when SCH >= 12. When SCH <= 11, these bits will indicate the channel number of current conversion result +1. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN0-AIN1 AIN2-AIN3 AIN4-AIN5 AIN6-AIN7 GND Positive voltage reference Temperature sensor AVDD/3
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ADCCON3 (0xB6) - ADC Control 3
Bit 7:6 Name Reset 00 R/W R/W Description Selects reference voltage used for the extra conversion 00 01 10 11 5:4 Internal 1.25V reference External reference on AIN7 pin AVDD pin External reference on AIN6-AIN7 differential input
EREF[1:0]
EDIV[1:0]
00
R/W
Sets the decimation rate used for the extra conversion. The decimation rate also determines the resolution and time required to complete the conversion. 00 01 10 11 64 dec rate (8 bits resolution) 128 dec rate (10 bits resolution) 256 dec rate (12 bits resolution) 512 dec rate (14 bits resolution)
3:0
ECH[3:0]
0000
R/W
Extra channel select. Selects the channel number of the extra conversion that is carried out after a conversion sequence has ended. If the ADC is not running, writing to these bits will trigger an immediate single conversion from the selected extra channel. The bits are automatically cleared when the extra conversion has finished. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN0-AIN1 AIN2-AIN3 AIN4-AIN5 AIN6-AIN7 GND Positive voltage reference Temperature sensor VDD/3
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13.8 Random Number Generator 13.8.1 Introduction The random number generator has the following features. * * Generate pseudo-random bytes which can be read by the CPU. Calculate CRC16 of bytes that are written to RNDH. * Seeded by value written to RNDL.
The random number generator is a 16-bit Linear Feedback Shift Register (LFSR) with polynomial X CRC16). It uses unrolling depending performs. The basic is shown below.
16
different levels of on the operation it version (no unrolling)
+ X 15 + X 2 + 1 (i.e.
15
+
14
13
12
11
10
9
8
7
6
5
4
3
2
+
1
0
in_bit
+
Figure 26: Basic structure of the Random Number Generator The random number generator is turned off when ADCCON1.RCTRL="11". 13.8.2 Random Operation Number Generator time the RNDL register is written, the 8 LSB of the LFSR is copied to the 8 MSB and the 8 LSBs are replaced with the new data byte that was written to RNDL. 13.8.2.3 CRC16 The LFSR can also be used to calculate the CRC value of a sequence of bytes. Writing to the RNDH register will trigger a CRC calculation. The new byte is processed from the MSB end and an 8x unrolling is used, so that a new byte can be written to RNDH every clock cycle. Note that the LFSR must be properly seeded by writing to RNDL, before the CRC calculations start. Commonly used seed values are 0x0000 or 0xFFFF. 13.8.3 Registers The random number generator registers are described in this section.
The operation of the random number generator is controlled through a combination of the ADCCON1.RCTRL bits and input signals from other modules. The current value of the 16-bit shift register in the LFSR can be read from the RNDH and RNDL registers. 13.8.2.1 Semi random sequence generation The LFSR is updated by setting ADCCON1.RCTRL="01". This will clock the LFSR once (no unrolling) and the ADCCON1.RCTRL bits will automatically be cleared when the operation has completed. 13.8.2.2 Seeding The LFSR is seeded from software by writing to the RNDL register twice. Each
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RNDL (0xBC) - Random Number Generator Data Low Byte
Bit [7:0] Name Reset 0xFF R/W R/W Description Random value/seed or CRC result, low byte When used for random number generation writing this register twice will seed the random number generator. Writing to this register copies the 8 LSBs of the LFSR to the 8 MSBs and replaces the 8 LSBs with the data value written. The value returned when reading from this register is the 8 LSBs of the LSFR. When used for random number generation, reading this register returns the 8 LSBs of the random number. When used for CRC calculations, reading this register returns the 8 LSBs of the CRC result.
RNDL[7:0]
RNDH (0xBD) - Random Number Generator Data High Byte
Bit [7:0] Name Reset 0xFF R/W R/W Description Random value or CRC result/input data, high byte When written, a CRC16 calculation will be triggered, and the data value written is processed starting with the MSB bit. The value returned when reading from this register is the 8 MSBs of the LSFR. When used for random number generation, reading this register returns the 8 MSBs of the random number. When used for CRC calculations, reading this register returns the 8 MSBs of the CRC result.
RNDH[7:0]
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13.9 AES Coprocessor
CC2510FX/CC2511Fx, data With the encryption can be performed using a dedicated coprocessor which supports Advanced Encryption Standard, AES. The coprocessor allows encryption/decryption to be performed with minimal CPU usage.
The coprocessor features: * * * * has the following
be padded with zeros when written to the coprocessor. 13.9.4 Interface to CPU The CPU communicates with the coprocessor using three SFR registers: * * * ENCCS, Encryption control and status register ENCDI, Encryption input register ENCDO, Encryption output register
ECB, CBC, CFB, OFB, CTR and CBCMAC modes. Hardware support for CCM mode 128-bits key and IV/Nonce DMA transfer trigger capability
Read/write to the status register is done by the CPU, while read/write the input/output register is intended for use together with direct memory access (DMA). Two DMA channels must be used, one for input data and one for output data. The DMA channels must be initialized before a start command is written to the ENCCS. Writing a start command generates a DMA trigger and the transfer is started. After each block is processed, an interrupt is generated. The interrupt is used to issue a new start command to the ENCCS. 13.9.5 Modes of operation ECB and CBC modes are performed as described in section 13.9.1 When using CFB, OFB and CTR mode, the 128 bits blocks are divided into four 32 bits blocks. 32 bits are loaded into the AES coprocessor and the resulting 32 bits are read out. This continues until all 128 bits are encrypted. The only time one has to consider this is if data is loaded/read directly using the CPU. When using DMA, this is handled automatically by the DMA triggers generated by the AES coprocessor. Both encryption and performed similarly. decryption are
13.9.1 AES Operation To encrypt a message, the following procedure must be followed: * * * Load key Load initialization vector (IV) Download and upload encryption/decryption. data for
The AES coprocessor works on blocks of 128 bits. A block of data is loaded into the coprocessor, encryption is performed and the result must be read out before the next block can be processed. Before each block load, a dedicated start command must be sent to the coprocessor. 13.9.2 Key and IV Before a key or IV/nonce load starts, an appropriate load key or IV must be issued to the coprocessor. When loading the IV it is important to also set the correct mode. A key load or IV load operation aborts any processing that could be running. The key, once loaded, stays valid until a key reload takes place. The IV must be downloaded before the beginning of each message (not block). Both key and IV are cleared by a reset. 13.9.3 Padding of input data AES works on blocks of 128 bits. If the last block contains less than 128 bits, it must
The CBC-MAC mode is a variant of the CBC mode. When performing CBC-MAC, data is downloaded to the coprocessor as one block at a time, except for the last block. Before the last block is loaded, the mode must be changed to CBC. The last block is then downloaded and the block uploaded will be the MAC value.
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CCM is a combination of CBC-MAC and CTR. Parts of the CCM must therefore be done in software. The following section gives a short explanation of the necessary steps to be done. 13.9.5.1 CBC-MAC When performing CBC-MAC encryption, data is only downloaded to the coprocessor in CBC-MAC mode except for the last block, one block at a time. Before the last block is loaded, the mode is changed to CBC. The last block is downloaded and the block uploaded is the message MAC. CBC-MAC decryption is similar to encryption. The message MAC uploaded Name B0
Byte Name 0 1 2 3 4
must be compared with the MAC to be verified. 13.9.5.2 CCM mode To encrypt a message under CCM mode, the following sequence can be conducted (key is already loaded): Message Authentication Phase This phase takes place during steps 1-6 shown in the following. (1) The software loads the IV with zeros. (2) The software creates the block B0. The layout of block B0 is shown in Figure 27. .
Designation First block for authentication in CCM mode
5 6 7 8 9 10 11 12 13 14 15
Flag
NONCE
L_M
Figure 27: Message Authentication Phase Block 0
There is no restriction on the NONCE value. L_M is the message length in bytes. The content of the Authentication Flag byte is described in Figure 28. Name FLAG/B0 Bit Name Value 0 7 Reserved x 6 A_Data x Designation
L is set to 6 in this example. So, L-1 is set to 5. M and A_Data can be set to any value.
Authentication Flag Field for CCM mode 5 x 4 (M-2)/2 x 1 0 3 2 1 L-1 1 0
Figure 28: Authentication Flag Byte (3) If some Additional Authentication Data (called a later) is needed (that is A_Data =1), the software creates the A_Data length field, called L(a) by : * (3a) If l(a)=0, (that is A_Data =0), then L(a) is the empty string. We note l(a) the length of a in octets. (3b) If 0 < l(a) < 216 - 28 , then L(a) is the 2-octets encoding of l(a).
*
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The Additional Authentication Data is appended to the A_Data length field L(a). The Additional Authentication Blocks is padded with zeros until the last Additional Authentication Block is full. There is no restriction on the length of a. AUTH-DATA = L(a) + Authentication Data + (zero padding) (4) The last block of the message is padded with 0s until full (that is if its length is not a multiple of 128). (5) The software concatenates the block B0, the Additional Authentication Blocks if any, and the message; Input message = B0 + AUTH-DATA + Message + (zero padding of message) (6) Once the input message authentication by CBC-MAC is finished, the software leaves the uploaded buffer contents unchanged (M=16), or keeps only the buffer's higher M bytes unchanged, while setting the lower bits to 0 (M != 16). The result is called T. Message Encryption (7) The software creates the key stream block A0. Note that L=6, with the current example of the CTR generation. The content is shown in Figure 29:
Name A0
Byte Name 0 1 2 3 4
Designation First CTR value for CCM mode
5 6 7 8 9 10 11 12 13 14 15
Flag
NONCE
CTR
Figure 29: Message Encryption Phase Block 0 Note that any value but zero works for the CTR value. The content of the Encryption Flag byte is described in Figure 30 Name FLAG/A0 Bit Name Value 0 7 Reserved 0 0 0 6 Designation Encryption Flag Field for CCM mode 5 4 0 1 0 3 2 1 L-1 1 0
Figure 30: Encryption Flag Byte (8) The software loads A0 by selecting a Load IV/Nonce command. To do so, it sets Mode to CFB or OFB at the same time it selects the Load IV/Nonce command. (9) The software calls a CFB or an OFB encryption on the authenticated data T. The uploaded buffer contents stay unchanged (M=16), or only its first M bytes stay unchanged, the others being set to 0 (M-16). The result is U, which will be used later. (10) The software calls a CTR mode encryption right now on the still padded message blocks. It does not have to reload the IV/CTR. (11) The encrypted authentication data U is appended to the encrypted message. This gives the final result, c. Result c = encrypted message(m) + U Message Decryption
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CCM Mode decryption In the coprocessor, the automatic generation of CTR works on 32 bits, therefore the maximum length of a message is 128 x 232 bits, that is 236 bytes, which can be written in a six-bit word. So, the value L is set to 6. To decrypt a CCM mode processed message, the following sequence can be conducted (key is already loaded): Message Parsing Phase (1) The software parses the message by separating the M rightmost octets, namely U, and the other octets, namely string C. (2) C is padded with zeros until it can fill an integer number of 128-bit blocks; (3) U is padded with zeros until it can fill a 128-bit block. (4) The software creates the key stream block A0. It is done the same way as for CCM encryption. (5) The software loads A0 by selected a Load IV/Nonce command. To do so, it sets Mode to CFB or OFB at the same time it selects the IV load. (6) The software calls a CFB or an OFB encryption on the encrypted authenticated data U. The uploaded buffer contents stay unchanged (M=16), or only its first M bytes stay unchanged, the others being set to 0 (M!=16). The result is T. (7) The software calls a CTR mode decryption right now on the encrypted message blocks C. It does not have to reload the IV/CTR. Reference generation Authentication tag The only difference is that the result is named MACTag (instead of T). Message Phase Authentication checking
The software compares T with MACTag. 13.9.6 Sharing the AES between layers coprocessor
The AES coprocessor is a common resource shared by all layers. The AES coprocessor can only be used by one instance one at a time. It is therefore necessary to implement some kind of software semaphore to allocate and deallocate the resource. 13.9.7 AES Interrupts The AES interrupt, ENC, is produced when encryption or decryption of a block is completed. The interrupt enable bit is IEN0.ENCIE and the interrupt flag is S0CON.ENCIF. 13.9.8 AES DMA Triggers There are two DMA triggers associated with the AES coprocessor. These are ENC_DW which is active when input data needs to be downloaded to the ENCDI register, and ENC_UP which is active when output data needs to be uploaded from the ENCDO register. The ENCDI and ENCDO registers should be set as destination and source locations for DMA channels used to transfer data to or from the AES coprocessor. 13.9.9 AES Registers The AES coprocessor registers have the layout shown in this section.
This phase is identical to the Authentication Phase of CCM encryption.
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ENCCS (0xB3) - Encryption Control and Status
Bit 7 6:4 Name Reset 0 000 R/W R0 R/W Description Not used, always read as 0 Encryption/decryption mode 000 001 010 011 100 101 110 111 3 CBC CFB OFB CTR ECB CBC MAC Not used Not used
MODE[2:0]
RDY
1
R
Encryption/decryption ready status 0 1 Encryption/decryption in progress Encryption/decryption is completed
2:1
CMD[1:0]
0
R/W
Command to be performed when a 1 is written to ST. 00 01 10 11 encrypt block decrypt block load key load IV/nonce
0
ST
0
R/W1 H0
Start processing command set by CMD. Must be issued for each command or 128 bits block of data. Cleared by hardware
ENCDI (0xB1) - Encryption Input Data
Bit 7:0 Name Reset 0x00 R/W R/W Description Encryption input data
DIN[7:0]
ENCDO (0xB2) - Encryption Output Data
Bit 7:0 Name Reset 0x00 R/W R/W Description Encryption output data
DOUT[7:0]
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13.10 Power Management This section describes the Power Management Controller. The Power Management Controller controls the use of power modes and clock control to achieve low-power operation. 13.10.1 Power Management Introduction The CC2510FX/CC2511Fx uses different operating modes, or power modes, to allow low-power operation. Ultra-lowpower operation is obtained by turning off power supply to modules to avoid static (leakage) power consumption and also by using clock gating to reduce dynamic power consumption. The various operating modes are enumerated and shall be designated as power modes (PMx). The power modes are: * PM0 Clock oscillators on, voltage regulator on PM1 32.768/34 kHz oscillators on, voltage regulator on PM2 32.768/34 kHz oscillators on, voltage regulator off PM3 All clock oscillators regulator off off, voltage high-speed oscillators are started. The device will run on the high speed RC oscillator until the high speed crystal oscillator has settled and has been selected. PM1 is used when the expected time until a wakeup event is relatively short since PM1 uses a fast power down/up sequence. 13.10.1.3 PM2 PM2 has the second lowest power consumption. In PM2 the power-on reset, external interrupts, 32.768/34 kHz oscillators and sleep timer peripherals are active. I/O pins retain the I/O mode and output value set before entering PM2. All other internal circuits are powered down. The voltage regulator is also turned off. When PM2 is entered, a power down sequence is run. PM2 is used when it is relatively long until the expected time of a wakeup event, since the power up/down sequence is relatively long. PM2 is typically entered when using the sleep timer as the wakeup event. 13.10.1.4 PM3 PM3 is used to achieve the operating mode with the lowest power consumption. In PM3 all internal circuits that are powered from the voltage regulator are turned off. The internal voltage regulator and all oscillators are also turned off. Power-on reset and external interrupts are the only functions that are operating in this mode. I/O pins retain the I/O mode and output value set before entering PM3. Only a reset or external interrupt condition will wake the device up and place it into PM0. The contents of RAM and registers are preserved in this mode. PM3 uses the same power down/up sequence as PM2. PM3 is used to achieve ultra low power consumption when waiting for an external event. 13.10.2 Power Management Control The required power mode is selected by the MODE bits in the SLEEP control
*
*
*
13.10.1.1 PM0 PM0 is the full functional mode of operation where the CPU and peripherals are active. The voltage regulator is turned on. PM0 is used for normal operation. 13.10.1.2 PM1 In PM1, the high-speed oscillators are powered down thereby halting the CPU and peripherals. The voltage regulator, the power-on reset, external interrupts, the 32.768/34 kHz oscillators and sleep timer peripherals are active. I/O pins retain the I/O mode and output value set before entering PM1. When PM1 is entered, a power down sequence is run. When the device is taken out of PM1 to PM0, the
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register. Setting the SFR register PCON.IDLE bit after setting the MODE bits, enters the selected power mode. An interrupt from port pins, or sleep timer (not PM3) or a power-on reset will wake the device and bring it into PM0 by resetting the MODE bits. 13.10.3 System Clock The system clock is derived from the selected main clock source, which is the high-speed (26/48 MHz) crystal oscillator or the high-speed (13 MHz) RC oscillator. The CLKCON.OSC bit selects the source of the main system clock. Note that to use the RF transceiver the high speed crystal oscillator must be selected and stable. When the SLEEP.XOSC_STB is 1, the 26/48 MHz crystal oscillator is stable and can be used as the source for the system clock. The oscillator not selected as the system clock source, will be set in power-down mode by setting SLEEP.OSC_PD to 1. Thus the high-speed RC oscillator may be turned off when the 26/48 MHz crystal oscillator has been selected as system clock source and vice versa. When SLEEP.OSC_PD is 0, both oscillators are powered up and running. The selected main clock source can be divided down by setting the CLKCON.CLKSPD register appropriately. Eight different system clock frequencies from 0.203 to 26 MHz for CC2510FX or from 0.1875 to 24 MHz for CC2511Fx can be used. 13.10.4 High-speed oscillators Two high speed oscillators are present in the device. The high-speed crystal oscillator startup time may be too long for some applications, therefore the device will run on the high-speed RC oscillator until crystal oscillator is stable. The highspeed RC oscillator consumes less power than the crystal oscillator, but since it is not as accurate as the crystal oscillator it can not be used for RF transceiver operation. 13.10.5 32.768/34 kHz oscillators Two low power oscillators are present in the device. By default the low power RC oscillator is enabled (see Table 12 on page 16). The low power RC oscillator consumes less power, but is less accurate than the 32.768 kHz crystal oscillator. When the high speed crystal oscillator is running the low power RC oscillator is continuously calibrated. It is calibrated to a frequency equal to high speed crystal frequency divided by 750. E.g. 34.67 kHz with 26 MHz crystal (CC2510FX) and 32 kHz with 24 MHz crystal (CC2511Fx). 13.10.6 Timer Tick generation The power management controller generates a tick or enable signal for the peripheral timers, thus acting as a prescaler for the timers. This is a global clock division for Timer 1, Timer 3 and Timer 4. The tick speed is programmed from 0.203 to 26 MHz for CC2510FX or from 0.1875 to 24 MHz for CC2511Fx by setting the CLKCON.TICKSPD register appropriately. Note: The CLKCON.TICKSPD register cannot be set higher than CLKCON.CLKSPD. 13.10.7 Data Retention In power modes PM2 and PM3 parts of SRAM will retain its contents. The content of internal registers is also retained in PM2/3. The XDATA memory locations 0xF0000xFFFF (4096 bytes) retains data in PM2/3. Please note one exception as given below. The XDATA memory locations 0xFDA20xFEFF (350 bytes) will lose all data when PM2/3 is entered. These locations will contain undefined data when PM0 is reentered. The registers which retain their contents are the CPU registers, peripheral registers and RF registers, therefore switching to the low-power modes PM2/3 appears transparent to software. 13.10.8 I/O and Radio I/O port pins P1_0 and P1_1 do not have internal pull-up/pull-down resistors. These
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pins should therefore be set as outputs or pulled high/low externally to avoid leakage current. To save power, the radio should be turned off when it is not used.
13.10.9 Power Management Registers This section describes the Power Management registers.
PCON (0x87) - Power Mode Control
Bit 7:2 1 0 Name Reset 0x00 0 0 R/W R/W R0 R0/W H0 Description Not used. Not used, always read as 0. Power mode control. Writing a 1 to this bit forces entry to the power mode set by SLEEP.MODE. This bit is always read as 0
IDLE
SLEEP (0xBE) - Sleep Mode Control
Bit 7 Name Reset 0 R/W R/W Description USB Enable (CC2511Fx). This bit is unused for CC2510FX. 0 - USB Disabled 1 - USB Enabled 6
USB_EN
XOSC_STB
0
R
26/48 MHz Crystal oscillator stable status: 0 - oscillator is not powered up or not yet stable 1 - oscillator is powered up and stable
5
HFRC_STB
0
R
High speed RC oscillator stable status: 0 - oscillator is not powered up or not yet stable 1 - oscillator is powered up and stable
4:3 2
RST[1:0] OSC_PD
XX 1
R R/W H0
Reserved. XOSC and HS RCOSC power down setting. The bit is cleared if the CLKCON.OSC bit is toggled. Also, if there is a calibration in progress and the CPU attempts to set the bit, the bit will be updated at the end of calibration: 0 - Both oscillators powered up 1 - Oscillator not selected by CLKCON.OSC bit powered down
1:0
MODE[1:0]
00
R/W
Sleep mode setting: 00 - Power mode 0 01 - Power mode 1 10 - Power mode 2 11 - Power mode 3
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CLKCON (0xC6) - Clock Control
Bit 7 Name Reset 1 R/W R/W Description 32 kHz clock oscillator select: 0 - 32.768 kHz crystal oscillator 1 - 34 kHz low power RC oscillator 6
OSC32K
OSC
1
R/W
Main clock oscillator select: 0 - 26/48 MHz crystal oscillator 1 - 13 MHz HF RC oscillator This setting will only take effect when the selected oscillator is powered up and stable. If the selected oscillator is not powered up, then writing this bit will power it up.
5:3
TICKSPD[2:0]
001
R/W
Timer ticks output setting. The value of TICKSPD cannot be higher than CLKSPD.
CC2510FX
000 001 010 011 100 101 110 111 2:0 26 MHz 13 MHz 6.5 MHz 3.25 MHz 1.625 MHz 812.5 kHz 406.25 kHz 203.125 kHz
CC2511Fx
24 MHz 12 MHz 6 MHz 3 MHz 1.5 MHz 750 kHz 325 kHz 162.5 kHz
CLKSPD[2:0]
001
R/W
Clock speed setting. When a new CLKSPD value is written, the new setting is read when the clock has changed.
CC2510FX
000 001 010 011 100 101 110 111 26 MHz 13 MHz 6.5 MHz 3.25 MHz 1.625 MHz 812.5 kHz 406.25 kHz 203.125 kHz
CC2511Fx
24 MHz 12 MHz 6 MHz 3 MHz 1.5 MHz 750 kHz 325 kHz 162.5 kHz
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13.11 Power On Reset The CC2510FX/CC2511Fx includes a Power On Reset (POR) in order to protect the memory contents during supply voltage variations and provide correct initialization during power-on. When power is initially applied to the CC2510FX/CC2511Fx the Power On Reset (POR) will hold the device in reset state until the supply voltage reaches above the Power On Reset voltage as defined in Table 5 on page 11. Figure 31 shows the POR operation with the 1.8V (typical) regulated supply voltage together with the active low reset signal shown in the bottom of the figure. The cause of the last reset can read from the register bits SLEEP.RST.
VOLT
1.8V REGULATED
UNREGULATED
POR RESET DEASSERT RISING VDD POR RESET ASSERT FALLING VDD
0 POR RESET
X
X
Figure 31 : Power On Reset Operation
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13.12 Watchdog Timer The watchdog timer (WDT) is intended as a recovery method in situations where the software hangs. The WDT shall reset the system when software fails to clear the WDT within a selected time interval. The watchdog can be used in applications that are subject to electrical noise, power glitches, electrostatic discharge etc., or where high reliability is required. If the watchdog function is not needed in an application, it is possible to configure the watchdog timer to be used as an interval timer that can be used to generate interrupts at selected time intervals. The features of the watchdog timer are as follows: * * * * * Four selectable timer intervals Watchdog mode Timer mode Interrupt request generation in timer mode Clock independent from system clock If the counter reaches the selected timer interval value, the watchdog timer generates a reset signal for the system. If a watchdog clear sequence is performed before the counter reaches the selected timer interval value, the counter is reset to 0x0000 and continues incrementing its value. The watchdog clear sequence consists of writing 0xA to WDCTL.CLR[3:0] followed by writing 0x5 to the same register bits within one half of a watchdog clock period. If this complete sequence is not performed, the watchdog timer generates a reset signal for the system. Note that as long as a correct watchdog clear sequence begins within the selected timer interval, the counter is reset when the complete sequence has been received. When the watchdog timer has been enabled in watchdog mode, it is not possible to change the mode by writing to the WDCTL.MODE bit. The timer interval value can be changed by writing to the WDCTL.INT[1:0] bits. Note that it is recommended that user software clears the watchdog timer at the same time as the timer interval value is changed, in order to avoid an unwanted watchdog reset. In watchdog mode, the WDT does not produce an interrupt request.
The WDT is configured as either a watchdog timer or as a timer for generalpurpose use. The operation of the WDT module is controlled by the WDCTL register. The watchdog timer consists of an 15-bit counter clocked by the 32.768 oscillator or 32 - 34 kHz rc clock. Note that the contents of the 15-bit counter is not user-accessible. 13.12.1 Watchdog mode The watchdog timer is disabled after a system reset. To set the WDT in watchdog mode the WDCTL.MODE bit is set to 0. The watchdog timer counter starts incrementing when the enable bit WDCTL.EN is set to 1. When the timer is enabled in watchdog mode it is not possible to disable the timer. Therfore, writing a 0 to WDCTL.EN has no effect if a 1 was already written to this bit when WDCTL.MODE was 0. The WDT can operate with a watchdog timer clock frequency of 32.768 kHz. This clock frequency gives time-out periods equal to 1.9 ms, 15.625 ms, 0.25 s and 1 s corresponding to the count value settings 64, 512, 8192 and 32768 respectively.
13.12.2
Timer mode
To set the WDT in normal timer mode, the WDCTL.MODE bit is set to 1. When register bit WDCTL.EN is set to 1, the timer is started and the counter starts incrementing. When the counter reaches the selected interval value, the timer will produce an interrupt request. In timer mode, it is possible to clear the timer contents by writing a 1 to WDCTL.CLR[0]. When the timer is cleared the contents of the counter is set to 0x0000. Writing a 0 to the enable bit WDCTL.EN stops the timer and writing 1 restarts the timer from 0x0000. The timer interval is set by the WDCTL.INT[1:0] bits. In timer mode, a
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reset will not be produced when the timer interval has been reached. 13.12.3 Watchdog Timer Example Figure 32 shows an example of periodical clearing of an active watchdog timer.
; clear watchdog timer MOV WDCTL,#ABh MOV WDCTL,#5Bh
Figure 32: WDT Example 13.12.4 Watchdog Timer Register This section describes the register for the Watchdog Timer.
WDCTL (0xC9) - Watchdog Timer Control
Bit 7:4 Name Reset 0000 R/W R/W Description Clear timer. When 0xA followed by 0x5 is written to these bits, the timer is loaded with 0x0. Note the timer will only be cleared when 0x5 is written within 0.5 watchdog clock period after 0xA was written. Writing to these bits when EN is 0 has no effect. These bits are always be read as 0000. Enable timer. When a 1 is written to this bit the timer is enabled and starts incrementing. Writing a 0 to this bit in timer mode stops the timer. Writing a 0 to this bit in watchdog mode has no effect. 0 1 2 Timer disabled (stop timer) Timer enabled
CLR[3:0]
3
EN
0
R/W
MODE
0
R/W
Mode select. This bit selects the watchdog timer mode. 0 1 Watchdog mode Timer mode
1:0
INT[1:0]
00
R/W
Timer interval select. These bits select the timer interval defined as a given number of 32.768 or 34 kHz oscillator periods. 00 01 10 11 clock period x 32768 (typical 1 s) clock period x 8192 (typical 0.25 s) clock period x 512 (typical 15.625 ms) clock period x 64 (typical 1.9 ms)
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13.13 USART USART0 and USART1 are serial communications interfaces that can be operated separately in either asynchronous UART mode or in synchronous SPI mode. The two USARTs have identical function, and are assigned to separate I/O pins. Refer to section 13.1 for I/O configuration. 13.13.1 UART mode For asynchronous serial interfaces, the UART mode is provided. In the UART mode the interface uses a two-wire interface consisting of the pins RXD and TXD. The UART mode of operation includes the following features: * * * * * * * 8 or 9 data bits Odd, even or no parity Configurable start and stop bit level Configurable LSB or MSB first transfer Independent interrupts receive and and transmit transmit transmitted on the TXDx output pin. The UxDBUF register is double-buffered. The UxCSR.ACTIVE bit goes high when the byte transmission starts and low when it ends. When byte transmission ends the UxCSR.TX_BYTE bit is set. An interrupt request is generated when the UxDBUF register is ready to accept new transmit data. This happens immediately after the transmission has been started, hence a new data byte value can be loaded into the data buffer while a byte is being transmitted. 13.13.1.2 UART Receive Data reception on the UART is initiated when a 1 is written to the UxCSR.RE bit. The UART will then search for a valid start bit on the RXDx input pin and set the UxCSR.ACTIVE bit high. When a valid start bit has been detected the received byte is shifted into the receive register. The UxCSR.RX_BYTE bit is set when the operation has completed, and a receive interrupt is generated. At the same time UxCSR.ACTIVE will go low. The received data byte is available through the UxDBUF register. When UxDBUF is read, UxCSR.RX_BYTE is cleared by hardware. 13.13.1.3 UART Character Format If the BIT9 and PARITY bits in register UxUCR are set high, parity generation and detection is enabled. The parity is computed and transmitted as the ninth bit, and during reception, the parity is computed and compared to the received ninth bit. If there is a parity error, the UxCSR.ERR bit is set high. This bit is cleared when UxCSR is read. The number of stop bits to be transmitted is set to one or two bits determined by the register bit UxUCR.SPB. The receiver will always check for one stop bit. If the first stop bit received during reception is not at the expected stop bit level, a framing error is signaled by setting register bit UxCSR.FE high. UxCSR.FE is cleared when UxCSR is read. The receiver will
Independent receive DMA triggers
Parity and framing error status
The UART mode provides full duplex asynchronous transfers, and the synchronization of bits in the receiver does not interfere with the transmit function. A UART byte transfer consists of a start bit, eight data bits, an optional ninth data or parity bit, and one or two stop bits. Note that the data transferred is referred to as a byte, although the data can actually consist of eight or nine bits. The UART operation is controlled by the USART Control and Status registers, UxCSR and the UART Control register UxUCR where x is the USART number, 0 or 1. The UART mode is UxCSR.MODE is set to 1. 13.13.1.1 UART Transmit A UART transmission is initiated when the USART Receive/Transmit Data Buffer, UxDBUF register is written. The byte is selected when
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check both stop bits when UxUCR.SPB is set. 13.13.2 SPI Mode This section describes the SPI mode of operation for synchronous communication. In SPI mode, the USART communicates with an external system through a 3-wire or 4-wire interface. The interface consists of the pins MOSI, MISO, SCK and SSN. Refer to section 13.1 for description of how the USART pins are assigned to the I/O pins. The SPI mode includes the following features: * * * Master and slave modes Configurable SCK polarity and phase Configurable LSB or MSB first transfer when At the end of the transfer, the received data byte is available for reading from the UxDBUF register. A transmit interrupt is generated when the unit is ready to accept another data byte for transmission. Since UxDBUF is doublebuffered, this happens just after the transmission has been initiated. 13.13.2.2 SPI Slave Operation An SPI byte transfer in slave mode is controlled by the external system. The data on the MOSI input is shifted into the receive register controlled by the serial clock SCK which is an input in slave mode. At the same time the byte in the transmit register is shifted out onto the MISO output. The UxCSR.ACTIVE bit goes high when the transfer starts and low when the transfer ends. Then the UxCSR.RX_BYTE and UxCSR.TX_BYTE bits are set and a receive interrupt is generated. The expected polarity and clock phase of SCK is selected by UxGCR.CPOL and UxGCR.CPHA as shown in Figure 33. The expected order of the byte transfer is selected by the UxGCR.ORDER bit. At the end of the transfer, the received data byte is available for reading from the UxDBUF register. The transmit interrupt is generated at the start of the operation. 13.13.2.3 Slave Select pin (SSN) When the USART is operating in SPI mode, configured as an SPI slave, the Slave Select (SSN) pin is an input to the SPI. When SSN is held low, the SPI slave is active and receives data on the MOSI input and outputs data on the MISO output. When SSN is held high, the SPI slave is inactive and will not receive data. In SPI master mode, the SSN pin is not used. When the device operates as an SPI master and a slave select signal is needed by an external SPI slave device, then a general purpose I/O pin should be used to implement the slave select signal function in software.
The SPI mode is selected UxCSR.MODE is set to 0.
In SPI mode, the USART can be configured to operate either as an SPI master or as an SPI slave by writing the UxCSR.SLAVE bit. 13.13.2.1 SPI Master Operation An SPI byte transfer in master mode is initiated when the UxDBUF register is written. The USART generates the SCK serial clock using the baud rate generator (see section 13.13.3) and shifts the provided byte from the transmit register onto the MOSI output. At the same time the receive register shifts in the received byte from the MISO input pin. The UxCSR.ACTIVE bit goes high when the transfer starts and low when the transfer ends. When the transfer ends, the UxCSR.RX_BYTE and UxCSR.TX_BYTE bits are set. A receive interrupt is generated when new received data is ready in the UxDBUF USART Receive/Transmit Data register. The polarity and clock phase of the serial clock SCK is selected by UxGCR.CPOL and UxGCR.CPHA as shown in Figure 33. The order of the byte transfer is selected by the UxGCR.ORDER bit.
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Figure 33: SPI Dataflow
13.13.3 Baud Rate Generation An internal baud rate generator sets the UART baud rate when operating in UART mode and the SPI master clock frequency when operating in SPI mode. The UxBAUD.BAUD_M[7:0] and UxGCR.BAUD_E[4:0] registers define the baud rate used for UART transfers and the rate of the serial clock for SPI transfers. The baud rate is given by the following equation: table also gives the difference in actual baud rate to standard baud rate value as a percentage error. The maximum baud rate for UART mode is F/16 when BAUD_E is 16 and BAUD_M is 0, and where F is the system clock frequency. The maximum generated SPI clock frequency in master SPI mode is F/2 when BAUD_E is 19 and BAUD_M is 0, and where F is the system clock frequency. Setting higher clock frequencies than this will give erroneous results. The maximum SPI bit rate supported in slave mode is F/8.
Baudrate =
where F is the system clock frequency set by the selected system clock source.
(256 + BAUD _ M ) 2 BAUD _ E F 2 28
The register values required for standard baud rates are shown in Table 45 for a typical system clock set to 26 MHz. The
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Baud rate (bps) 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 230400 UxBAUD.BAUD_M 131 131 131 34 131 34 131 34 131 34 34 UxGCR.BAUD_E 6 7 8 9 9 10 10 11 11 12 13 Error (%) 0.04 0.04 0.04 0.13 0.04 0.13 0.04 0.13 0.04 0.13 0.13
Table 45: Commonly used baud rate settings for 26 MHz system clock (CC2510FX)
Baud rate (bps) 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 230400
UxBAUD.BAUD_M 163 163 163 59 163 59 163 59 163 59 59
UxGCR.BAUD_E 6 7 8 9 9 10 10 11 11 12 13
Error (%) 0.08 0.08 0.09 0.13 0.10 0.14 0.10 0.14 0.10 0.14 0.14
Table 46: Commonly used baud rate settings for 24 MHz system clock (CC2511Fx) The USART interrupt enable bits are found in the IEN0 and IEN2 registers. The interrupt flags are located in the TCON and IRCON2 registers. Refer to section 12.7 on page 49 for details of these registers. The interrupt enables and flags are summarized below. Interrupt enables: * * USART0 RX : IEN0.URX0IE USART1 RX : IEN0.URX1IE
13.13.4 USART flushing The current operation can be aborted by setting the UxUCR.FLUSH register bit. This event will immediately stop the current operation and clear all data buffers. 13.13.5 USART Interrupts Each USART has two interrupts. These are the RX complete interrupt (URXx) and the TX complete interrupt (UTXx).
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* * * * * * USART0 TX : IEN2.UTX0IE USART1 TX : IEN2.UTX1IE Refer to Table 42 on page 90 for an overview of the DMA triggers. 13.13.7 USART Registers The registers for the USART are described in this section. For each USART there are five registers consisting of the following (x refers to USART number i.e. 0 or 1): * * * * * UxCSR USART x Control and Status UxUCR USART x UART Control UxGCR USART x Generic Control UxDBUF USART x Receive/Transmit data buffer UxBAUD USART x Baud Rate Control
Interrupt flags: USART0 RX : TCON.URX0 USART1 RX : TCON.URX1 USART0 TX : IRCON2.UTX0 USART1 TX : IRCON2.UTX1
13.13.6 USART DMA Triggers There are two DMA triggers associated with each USART. The DMA triggers are activated by RX complete and TX complete events i.e. the same events as the USART interrupt requests. A DMA channel can be configured using a USART Receive/Transmit buffer, UxDBUF, as source or destination address.
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U0CSR (0x86) - USART 0 Control and Status
Bit 7 Name MODE Reset 0 R/W R/W Description USART mode select 0 1 6 RE 0 R/W SPI mode UART mode
UART receiver enable 0 1 Receiver disabled Receiver enabled
5
SLAVE
0
R/W
SPI master or slave mode select 0 1 SPI master SPI slave
4
FE
0
R/W0
UART framing error status 0 1 No framing error detected Byte received with incorrect stop bit level
3
ERR
0
R/W0
UART parity error status 0 1 No parity error detected Byte received with parity error
2
RX_BYTE
0
R/W0
Receive byte status 0 1 No byte received Received byte ready
1
TX_BYTE
0
R/W0
Transmit byte status 0 1 Byte not transmitted Last byte written to Data Buffer register transmitted
0
ACTIVE
0
R
USART transmit/receive active status 0 1 USART idle USART busy in transmit or receive mode
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U0UCR (0xC4) - USART 0 UART Control
Bit 7 6 5 Name Reset 0 0 0 R/W R0/W1 R/W R/W Description Flush unit. When set, this event will immediately stop the current operation and return the unit to idle state. Reserved. Must be written as 0. UART data bit 9 contents. This value is used when 9 bit transfer is enabled. When parity is disabled the value written to D9 is transmitted as the bit 9 when 9 bit data is enabled. If parity is enabled then this bit sets the parity level as follows. 0 1 4 Even parity Odd parity
FLUSH D9
BIT9
0
R/W
UART 9-bit data enable. When this bit is 1, data is 9 bits and the contents of data bit 9 is given by D9 and PARITY. 0 1 8 bits transfer 9 bits transfer
3
PARITY
0
R/W
UART parity enable. 0 1 Parity disabled Parity enabled
2
SPB
0
R/W
UART number of stop bits. Selects the number of stop bits to transmit 0 1 1 stop bit 2 stop bits
1
STOP
1
R/W
UART stop bit level 0 1 Low stop bit High stop bit
0
START
0
R/W
UART start bit level. The polarity of the idle line is assumed to be the opposite of the selected start bit level. 0 1 Low start bit High start bit
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U0GCR (0xC5) - USART 0 Generic Control
Bit 7 Name Reset 0 R/W R/W Description SPI clock polarity 0 1 6 Negative clock polarity Positive clock polarity
CPOL
CPHA
0
R/W
SPI clock phase 0 Data is output on MOSI when SCK goes from CPOL inverted to CPOL, and data input is sampled on MISO when SCK goes from CPOL to CPOL inverted. Data is output on MOSI when SCK goes from CPOL to CPOL inverted, and data input is sampled on MISO when SCK goes from CPOL inverted to CPOL.
1
5
ORDER
0
R/W
Bit order for transfers 0 1 LSB first MSB first
4:0
BAUD_E[4:0]
0x00
R/W
Baud rate exponent value. BAUD_E along with BAUD_M decides the UART baud rate and the SPI master SCK clock frequency
U0DBUF (0xC1) - USART 0 Receive/Transmit Data Buffer
Bit 7:0 Name Reset 0x00 R/W R/W Description USART receive and transmit data. When writing this register the data written is written to the internal transmit data register. When reading this register, the data from the internal read data register is read.
DATA[7:0]
U0BAUD (0xC2) - USART 0 Baud Rate Control
Bit 7:0 Name Reset 0x00 R/W R/W Description Baud rate mantissa value. BAUD_E along with BAUD_M decides the UART baud rate and the SPI master SCK clock frequency
BAUD_M[7:0]
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U1CSR (0xF8) - USART 1 Control and Status
Bit 7 Name MODE Reset 0 R/W R/W Description USART mode select 0 1 6 RE 0 R/W SPI mode UART mode
UART receiver enable 0 1 Receiver disabled Receiver enabled
5
SLAVE
0
R/W
SPI master or slave mode select 0 1 SPI master SPI slave
4
FE
0
R/W0
UART framing error status 0 1 No framing error detected Byte received with incorrect stop bit level
3
ERR
0
R/W0
UART parity error status 0 1 No parity error detected Byte received with parity error
2
RX_BYTE
0
R/W0
Receive byte status 0 1 No byte received Received byte ready
1
TX_BYTE
0
R/W0
Transmit byte status 0 1 Byte not transmitted Last byte written to Data Buffer register transmitted
0
ACTIVE
0
R
USART transmit/receive active status 0 1 USART idle USART busy in transmit or receive mode
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U1UCR (0xFB) - USART 1 UART Control
Bit 7 6 5 Name Reset 0 0 0 R/W R0/W1 R/W R/W Description Flush unit. When set, this event will immediately stop the current operation and return the unit to idle state. Reserved. Must be written as 0. UART data bit 9 contents. This value is used 9 bit transfer is enabled. When parity is disabled the value written to D9 is transmitted as the bit 9 when 9 bit data is enabled. If parity is enabled then this bit sets the parity level as follows. 0 1 4 Even parity Odd parity
FLUSH D9
BIT9
0
R/W
UART 9-bit data enable. When this bit is 1, data is 9 bits and the contents of data bit 9 is given by D9 and PARITY. 0 1 8 bits transfer 9 bits transfer
3
PARITY
0
R/W
UART parity enable. 0 1 Parity disabled Parity enabled
2
SPB
0
R/W
UART number of stop bits. Selects the number of stop bits to transmit 0 1 1 stop bit 2 stop bits
1
STOP
1
R/W
UART stop bit level 0 1 Low stop bit High stop bit
0
START
0
R/W
UART start bit level. The polarity of the idle line is assumed to be the opposite of the selected start bit level. 0 1 Low start bit High start bit
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U1GCR (0xFC) - USART 1 Generic Control
Bit 7 Name Reset 0 R/W R/W Description SPI clock polarity 0 1 6 Negative clock polarity Positive clock polarity
CPOL
CPHA
0
R/W
SPI clock phase 0 Data is output on MOSI when SCK goes from CPOL inverted to CPOL, and data input is sampled on MISO when SCK goes from CPOL to CPOL inverted. Data is output on MOSI when SCK goes from CPOL to CPOL inverted, and data input is sampled on MISO when SCK goes from CPOL inverted to CPOL.
1
5
ORDER
0
R/W
Bit order for transfers 0 1 LSB first MSB first
4:0
BAUD_E[4:0]
0x00
R/W
Baud rate exponent value. BAUD_E along with BAUD_M decides the UART baud rate and the SPI master SCK clock frequency
U1DBUF (0xF9) - USART 1 Receive/Transmit Data Buffer
Bit 7:0 Name Reset 0x00 R/W R/W Description USART receive and transmit data. When writing this register the data written is written to the internal transmit data register. When reading this register, the data from the internal read data register is read.
DATA[7:0]
U1BAUD (0xFA) - USART 1 Baud Rate Control
Bit 7:0 Name Reset 0x00 R/W R/W Description Baud rate mantissa value. BAUD_E along with BAUD_M decides the UART baud rate and the SPI master SCK clock frequency
BAUD_M[7:0]
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13.14 I2S The CC2510FX/CC2511Fx provides an industry standard I2S interface. The I2S interface can be used to transfer digital audio samples between the CC2510FX/CC2511Fx and an external audio device, eg. audio DAC, audio DSP. The I2S interface can be configured to operate as master or slave and may use mono as well as stereo samples. When mono mode is enabled, the same audio sample will be used for both channels. Both full and half duplex is supported and automatic -Law compression and expansion can be used. The I2S interface consists of 4 signals: * * * * Continous Serial Clock (SCK) Word Select (WS) Serial Data In (RX) Serial Data Out (TX) When the module is in master mode, it drives the SCK and WS lines. When the I2S interface is in slave mode, these lines are driven by an external master. The data on the serial data lines is transferred most significant bit first with one bit per SCK cycle. The WS signal selects the channel of the currently transferred word (left = 0, right = 1). It also determines the length of each word. There is a transition on the WS line one bit time before the first word is transferred and before the last bit of each word. Figure 34 shows the I2S signaling. Only a single serial data signal is shown in this figure. The SD signal could be the RX or TX signal depending on the direction of the data. The sample in the data buffer is inverted before being sent onto the bus. Likewise, the bits received are inverted before they are loaded into the data buffer.
SCK
WS
SD SAMPLE n-1, RIGHT CHANNEL
MSB SAMPLE n, LEFT CHANNEL
LSB
MSB SAMPLE n+1, RIGHT CHANNEL
LSB
MSB
Figure 34 I2S Digital Audio Signaling The I2S interrupt enable bits are found in the I2SCFG0 register. The interrupt flags are located in the I2SSTAT register. The interrupt enables and flags are summarized below. Interrupt enables: * * * * I2S RX: I2SCFG0.RXIEN I2S TX: I2SCFG0.TXIEN
13.14.1 Enabling I2S The I2SCFG0.ENAB bit must be set to enable the I2S transmitter/receiver. However, when I2SCFG0.ENAB is not set, the I2S can still be used as a stand-alone -Law compression/expansion engine. Refer to section 13.14.12 on page 162 for more details about this. 13.14.2 I2S Interrupts The I2S has two RX and TX interrupts: * * I2S RX complete interrupt (I2SRX) I2S TX complete interrupt (I2STX)
Interrupt flags: I2S RX: I2SSTAT.RXIRQ I2S TX: I2SSTAT.TXIRQ
A TX interrupt is generated when the internal TX buffer is empty and the I2S
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fetches the new data previously written to the I2SDATH:I2SDATL registers. The TX interrupt flag, I2SSTAT.TXIRQ, is cleared when I2SDATH register is written. An RX interrupt is generated when the internal RX buffer is full and the contents of the RX buffer is copied to the pair of internal data registers that can be read from the I2SDATH:I2SDATL registers. The RX interrupt flag, I2SSTAT.TXIRQ, is cleared when the I2SDATH register is read. Notice that interrupts will also be generated if the corresponding RXIRQ or TXIRQ flags are set from software. The I2S shares interrupt vector with USART 1. Refer to section 12.7 on page 49 for more details about interrupts. 13.14.3 I2S DMA Triggers There are two DMA triggers associated with the I2S interface. The DMA triggers are activated by RX complete and TX complete events, i.e. the same events as the I2S interrupt requests. The DMA triggers are not masked by the interrupt enable bits, I2SCFG0.RXIEN and I2SCFG0.TXIEN. A DMA channel thus can be configured using the I2S receive/transmit data registers, I2SDATH:I2SDATL, as source or destination address and use the I2S DMA triggers. Notice that I2SRX / ADC_CH6 and I2STX / ADC_CH7 DMA trigger pairs use the same DMA trigger numbers. Thus, only one of I2SRX and ADC_CH6 and one of I2STX and ADC_CH7 can be used simultaneously. On the CC2511Fx ADC channels 7 and 8 cannot be used since P0_6 and P0_7 I/O pins are not available. Refer to Table 42 on page 90 for an overview of the DMA triggers. 13.14.4 Underflow/Overflow If the I2S attempts to read from internal TX buffer when it is empty, underflow condition occurs. The I2S then continue to read from the data in TX buffer, and the TXUNF flag of I2SSTAT register will be set. the an will the the condition occurs. The contents of the RX buffer will be overwritten and the RXOVF flag of the I2SSTAT register will be set. Thus, when debugging an application, software may check for underflow/overflow when an interrupt is generated or when the application completes. The TXUNF/RXOVF flags should be cleared in software. 13.14.5 Writing a word (TX) When each sample fits into a single byte or -Law compressed samples (always 8 bits) are written, i.e. -Law expansion is enabled, only the I2SDATH register needs to be written. When each sample is more than 8 bits the low byte must be written to the I2SDATL register before the high byte is written to the I2SDATH register. Thus, writing the I2SDATH register signifies the completion of the write operation. When the I2S is configured to send stereo, i.e. I2SCFG0.TXMONO is 0, the I2SSTAT.TXLR flag can be used to determine whether the left- or rightchannel sample is to be written to the data registers. 13.14.6 Reading a word (RX) If each sample fits into a single byte or Law compression is enabled, only the I2SDATH register needs to be read. When each sample is more than 8 bits the low byte must be read from the I2SDATL register before the high byte is being read from the I2SDATH register. Thus, reading from the I2SDATH register signifies the completion of the read operation. When the I2S is configured to receive stereo, i.e. I2SCFG0.RXMONO is 0, the I2SSTAT.RXLR flag can be used to determine whether the sample currently in the data registers is a left- or right-channel sample. 13.14.7 Full vs. half duplex The I2S interface supports full duplex and half duplex operation.
If the I2S attempts to write to the internal RX buffer while it is full, an overflow
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In full duplex both the RX and TX lines will be used. Both the I2SCFG0.TXIEN and I2SCFG0.RXIEN interrupt enable bits must be set if interrupts are used and both the DMA triggers I2STX and I2SRX may be used. When half duplex is used only one of the RX and TX lines are typically connected. Only the appropriate interrupt flag should be set and only one of the DMA triggers should be used. 13.14.8 Master Mode The I2S is configured as a master device by setting I2SCFG0.MASTER to 1. In master mode the SCK and WS signals are generated by the I2S. 13.14.8.1 Clock Generation When the I2S is configured as master, the frequency of the SCK clock signal must be set to match the sample rate. The clock frequency must be set before master mode is enabled. SCK is generated by dividing the system clock using a fractional clock divider. The amount of division is given by the 15 bit numerator, NUM and 9-bit denominator, DENOM as shown in the following formula: where
NUM > 3.35 DENOM
Where Fclk is the system clock frequency and Fsck is the I2S SCK sample clock frequency. The numerator and denominator are set by writing to the clock configuration registers I2SCLKF0, I2SCLKF1 and I2SCLKF2. Please note that to stay within the timing requirements of the I2S specification [3], a minimum value of 3.35 should be used for the (NUM / DENOM) fraction. The fractional divider is made such that most normal sample rates should be supported for most normal word sizes with a 24 MHz system clock frequency (CC2511Fx). Examples of supported configurations for a 24 MHz CLK is given in Table 47. Table 48 shows the configuration values for a 26 MHz system clock frequency. Notice that the generated I2S frequency is not exact for the 44.1 kHz, 16 bits word size configuration at 26 MHz. The numbers are calculated using the following formulas, where Fs is the sample rate and W is the word size:
Fs =
Fsck =
Fclk NUM 2( ) DENOM
CLKDIV 93.75 46.875 8.503401 7.8125
Fsck 2 *W
Fclk NUM = DENOM 4 * W * Fs
I2SCLKF0 0x04 0x08 0x93 0x10 Exact yes yes yes yes
CLKDIV =
Fsck (kHz) 8 8 44.1 48
Word Size (W) 8 16 16 16
I2SCLKF2 0x01 0x01 0x04 0x00
I2SCLKF1 0x77 0x77 0xE2 0x7D
Table 47 Example I2S Clock Configurations (CC2511Fx, 24 MHz)
Fsck (kHz) 8 8
Word Size (W) 8 16
CLKDIV 101.5625 50.78125
I2SCLKF2 0x06 0x06
I2SCLKF1 0x59 0x59
I2SCLKF0 0x10 0x20
Exact yes yes
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44.1 48 16 16 9.21201 8.46354 0x8A 0x06 0x2F 0x59 0x1B 0xC0 no yes
Table 48 Example I2S Clock Configurations (CC2510FX, 26 MHz) audio data in both channels and the left channel is the default mono channel. To send mono samples, set the I2SCFG0.TXMONO bit to 1. Each word will then be repeated in both channels before a new word is fetched from the data registers. This is to enable sending a mono audio signal to a stereo audio sink device. 13.14.11 Word Counter
13.14.8.2 Word Size The word size must be set before master mode is enabled. The word size is the number of bits used for each sample and can be set to a value between 1 and 33. To set the word size, write word size - 1 to the I2SCFG.WORDS[4:0] bits. Setting the word size to a value of 17 or more causes the I2S to pad each word with 0's in the least significant bits since the data registers provide maxmum 16 bits. This feature allows samples to be sent to an I2S device that takes a higher resolution than 16 bits. If the size of received samples exceeds 16 bits, only the 16 most significant bits will be put in the data registers and the remaining low order bits will be discarded. 13.14.9 Slave Mode The I2S is configured as a slave device by setting I2SCFG0.MASTER to 0. When in slave mode the SCK and WS signals are generated by an external I2S master and are inputs to the I2S interface. 13.14.9.1 Word Size When the I2S operates in slave mode, the word size is determined by the master that generates the WS signal. The I2S will provide bits from the internal 16-bit buffer until the buffer is empty. If the buffer becomes empty and the master still requests more bits, the I2S will send 0's (low order bits). If more than 16 bits are being received, the low order bits are discarded. 13.14.10 The I2S samples. also Mono supports mono audio
The I2S contains a 10-bit word counter that counts the number of transitions on the WS line since the last time the word counter was cleared. Triggers are used to clear the word counter. When a trigger occurs or software writes any value to the I2SWCNT register, the current value of the word counter is copied into the WCNT[9:0] field in the I2SWCNT/I2SSTAT registers and the word counter is cleared. Three triggers can be used to copy/clear the word counter. * * * USB SOF: USB Start of Frame. Occurs every ms. T1_CH0: Timer channel 0 1, compare,
IOC_1: IO pin input transition
When the I2S is configured not to use any trigger, the word counter can only be copied/cleared from software. The I2SCFG1.TRIGNUM[1:0] selects the trigger source. field
The word counter will saturate if it reaches its maximum value. Software should configure the trigger-interval and samplerate to ensure this never happens.
CC2511Fx: The word counter is typically
used to calculate the average sample rate over a long period of time (e.g. 1 second) needed by adaptive isochronous USB endpoints. The USB SOF event must then be used as trigger.
To receive mono samples, set the I2SCFG0.RXMONO bit to 1. Words from the right channel will then not be read into the data registers. This feature is included because some mono devices repeat their
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13.14.12 -Law compression and expansion The I2S interface can be configured to perform -Law compression and expansion. -Law compression is enabled by setting the I2SCFG0.ULAWC bit to 1 and -Law expansion is enabled by setting the I2SCFG0.ULAWE bit to 1. When the I2S interface is enabled, i.e. the I2SCFG0.ENAB bit is 1, and -Law expansion is enabled, every byte of -Law compressed data written to the I2SDATH register is expanded to a 16-bit sample before being transmitted. When the I2S interface is enabled and -Law compression is enabled each sample received is compressed to an 8-bit -Law sample and put in the I2SDATH register. When the I2S interface is disabled, i.e. the I2SCFG0.ENAB bit is 0, it can still be used to perform -Law compression/expansion for other resources in the system. To perform an expansion, the I2SCFG0.ULAWE must be set and the I2SCFG0.ULAWC bit must be cleared. Then write a byte of compressed data to the I2SDATH register. The expansion takes one clock cycle to perform, and then the result can
XDATA Address 0xDF40 0xDF41 0xDF42 0xDF43 0xDF44 0xDF45 0xDF46 0xDF47 0xDF48 Register I2SCFG0 I2SCFG1 I2SDATL I2SDATH I2SWCNT I2SSTAT I2SCLKF0 I2SCLKF1 I2SCLKF2 Description I2S Configuration Register 0 I2S Configuration Register 1 I2S Data Low Byte I2S Data High Byte I2S Word Count Register I2S Status Register I2S Clock Configuration Register 0 I2S Clock Configuration Register 1 I2S Clock Configuration Register 2
be read from the I2SDATH:I2SDATL registers. To perform a compression the I2SCFG0.ULAWC bit must be set and the I2SCFG0.ULAWE bit must be cleared. To start the compression, write a uncompressed 16-bit sample to the I2SDATH:I2SDATL registers. The compression takes one clock cycle to perform, and then the result can be read from the I2SDATH register. Only one of the flags I2SCFG0.ULAWC and I2SCFG0.ULAWE should be set when the I2S interface is used without the I2SCFG0.ENAB bit is set. 13.14.13 I2S Registers
This section describes all I2S registers used for control and status for the I2S. The USB registers reside in XDATA memory space in the region 0xDF40-0xDF48. Table 49 gives an overview of register addresses while the remaining tables in this section describe each register. Notice that the reset values for the registers reflect a configuration with 16-bit stereo samples and 44.1 kHz sample rate. The I2S is not enabled at reset.
Table 49 Overview of I2S Registers
0xDF40: I2SCFG0 - I2S Configuration Register 0
Bit 7 Field Name Reset 0 R/W R/W Description Transmit interrupt enable. 0 interrupts are disabled
TXIEN
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Bit Field Name Reset R/W Description 1 6 interrupts are enabled
RXIEN
0
R/W
Receive interrupt enable. 0 1 interrupts are disabled interrupts are enabled
5
ULAWE
0
R/W
-Law expansion enable bit. Set to enable expansion of data to transmit when ENAB is set, or to expand data written to I2SDATH when ENAB is cleared. -Law compression enable bit. Set to enable compression of data received when ENAB is set, or to compress data written to I2SDATH:I2SDATL when ENAB is cleared. TX mono enable. If this bit is set, each sample of audio data will be repeated in both channels before a new sample is fetched. This is to enable sending a mono signal to a stereo audio sink device. RX mono enable. If this bit is set, data from the right channel will be discarded, i.e. not be read into the data registers. This feature is included because some mono devices repeat their audio data in both channels and left is the default mono channel. The master bit indicates if the I2S should generate the CLK and WS signals or if it should read them from the pads. The bit enables the I2S interface. Notice that this bit must not be set if the I2S is to be used as a -Law compression/expansion unit.
4
ULAWC
0
R/W
3
TXMONO
0
R/W
2
RXMONO
0
R/W
1
MASTER
0
R/W
0
ENAB
0
R/W
0xDF41: I2SCFG1 - I2S Configuration Register 1
Bit 7:3 Field Name Reset 0x0F R/W R/W Description This field gives the word size - 1. The word size is the bit-length of one sample for one channel. Used to generate the WS signal when in master mode. Reset value 0x0F give 15 + 1 = 16 bit samples. 2:1
WORDS[4:0]
TRIGNUM[1:0]
00
R/W
Word counter copy and clear trigger to use. When zero, the word counter can only be cleared by software. 0 - No trigger 1 - USB SOF 2 - IOC_1 3 - T1_CH0
0
IOLOC
0
R/W
The pin locations for the I2S signals. This bit selects between the two alternavie pin mapping alternatives. Refer to Table 41 for an overview of pin locations. 0 - Alt. 1 in Table 41 is used 1 - Alt. 2 in Table 41 is used
0xDF42: I2SDATL - I2S Data Low Byte
Bit Field Name Reset R/W Description
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Bit 7:0 Field Name Reset 0x00 R/W R/W Description Data register low byte. If the I2SDATL register is not written between two writes of the I2SDATH register, the low byte of the TX register will be cleared.
I2SDAT[7:0]
0xDF43: I2SDATH - I2S Data High Byte
Bit 7:0 Field Name Reset 0x00 R/W R/W Description Data register high byte. When this register is read, the RXIRQ bit of the I2SSTAT register is cleared and the RX buffer is considered empty. When this register is written, the TXIRQ bit of the I2SSTAT register is cleared and the TX buffer is considered full.
I2SDAT[15:8]
0xDF44: I2SWCNT - I2S Word Count Register
Bit 7:0 Field Name Reset 0x00 R/W R/W Description This register contains the 8 low order bits of the 10bit nternal word counter at the time the last trigger specified by I2SCFG1.TRIGNUM occurred. If this register is written (any value), the value of the internal word counter is copied into this register and the internal word counter is cleared. Refer to section 13.14.11 for details about how to use this register.
WCNT[7:0]
0xDF45: I2SSTAT - I2S Status Register
Bit 7 6 5 4 3 Field Name Reset 0 0 0 0 0 R/W R/W R/W R R R/W H0 2 Description Tx buffer underflow. This bit must be cleared by software. Rx buffer overflow. This bit must be cleared by software. Left (=0) or right (=1) channel should be placed in transmit buffer. Left (=0) or right (=1) channel currently in receive buffer. Interrupt flag indicating that a tx interrupt request has not been serviced. This bit is cleared by hardware when the I2SDATH register is written. Interrupt flag indicating that an rx interrupt request has not been serviced. This is cleared by hardware when the I2SDATH register is read. Upper 2 bits of the copy of the 10-bit internal word counter at the time of the last trigger.
TXUNF RXOVF TXLR RXLR TXIRQ
RXIRQ
0
R/W H0
1:0
WCNT[9:8]
00
R
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0xDF46: I2SCLKF0 - I2S Clock Configuration Register 0
Bit 7:0 Field Name Reset 0x93 R/W R/W Description The clock division denominator low bits
DENOM[7:0]
0xDF47: I2SCLKF1 - I2S Clock Configuration Register 1
Bit 7:0 Field Name Reset 0xE2 R/W R/W Description Clock division numerator low bits
NUM[7:0]
0xDF48: I2SCLKF2 - I2S Clock Configuration Register 2
Bit 7 6:0 Field Name Reset 0 0x04 R/W R/W R/W Description Clock division denominator high bits Clock division numerator high bits.
DENOM[8] NUM[14:8]
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13.15 USB Controller Note: The USB controller is only available on the CC2511Fx. The CC2511Fx contains a Full-Speed USB 2.0 compatible function controller for serial communication with a PC or other equipment with USB host functionality. Note: This section will focus on describing the functionality of the USB Controller. Thus, it is assumed that the reader has a good understanding of USB and is familiar with the terms and concepts used. Refer to the Universal Serial Bus Specification for details. Standard USB nomenclature is used regaring IN and OUT. I.e, IN is always into the host (PC) and OUT is out of the host (into CC2511Fx) The USB Controller monitors the USB bus for relevant activity and handles packet transfer. The USB function will always operate as a slave on the USB bus. A packet can therefore only be sent (or received) when the USB host sends a request in the form of a token. Appropriate response to USB interrupts and loading/unloading of packets into/from endpoint FIFOs is the responsibility of the firmware. The firmware must be able to reply correctly to all standard requests from the USB host and work according to the protocol implemented in the driver on the PC. The USB Controller has the following features: * * Full-Speed operation (up to 12 Mbps) 5 endpoints (in addition to endpoint 0) that can be used as IN, OUT or IN/OUT and can be configured as Bulk, Interrupt or Isochronous. 1 KB SRAM FIFO available for storing USB packets Endpoints supporting packet sizes from 8 - 512 bytes Support for double buffering of USB packets
* * *
Figure 35 shows a block diagram of the USB Controller. The USB PHY is the physical interface with input and output drivers. The USB SIE is the Serial Interface Engine which controls the packet transfer to/from the endpoints. The USB Controller is connected to the rest of the system through the Memory Arbiter.
USB Controller EP0 EP1 DP USB PHY DM USB SIE EP3 EP4 EP5 EP2 Memory Arbiter
1 KB SRAM (FIFOs)
Figure 35: USB Controller block diagram
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13.15.1 USB Registers The operation through a set USB registers memory space page 36. of the USB is configured of USB registers. These are mapped to XDATA as shown in Figure 10 on interrupt routine must also handle Port 2 interrupts if they are used. The interrupt routine should read all the interrupt flag registers and take action depending on the status of the flags. The interrupt flag registers will be cleared when they are read. The interrupt flags must therefore be saved in memory (typically in a local variable on the stack) to be used in multiple operations. To enable USB interrupts IEN2.P2IE must be set to 1. It is important that the P2IFG register is cleared and then the IRCON2.P2IF bit is cleared at the end of the USB interrupt service routine after the interrupt flags have been read. This allows new USB/P2 interrupts to be detected. Refer to Table 33 for a complete list of interrupts and section 12.7 for more details about interrupts. 13.15.4.1 USB Resume Interrupt Bit 7 of Port 0 is used to wake up the CC2511Fx from PM1/suspend when resume signaling has been detected on the USB bus. IEN1.P0IE must therefore be set to 1 to enable P0 interrupts. PICTL.P0IENH must be set to 1 to enable interrupts on P0[7:4] and PICTL.P0ICON must be 0 to enable interrupts on rising edge. The P0 interrupt routine should check bit 7 of P0IFG and resume if this bit is set. Notice that bit 7 and bit 6 of Port 0 are not available as external ports on CC2511Fx. If PM1 is entered from within an interrupt routine (typically the USB/P2 interrupt routine) due to a suspend interrupt, it is important that the priority of the P0 interrupt is set higher than the interrupt that entered PM1. See section 13.15.9 for more details about suspend and resume. 13.15.5 Endpoint 0 Endpoint 0 (EP0) is a bi-directional control endpoint. A USB function is required to implement a control endpoint at endpoint 0. During the enumeration phase all communication is performed across this endpoint. Before the USBADDR register has been set (to a value other than 0), the USB Controller will only be able to communicate through endpoint 0. Setting the USBADDR register will bring the USB function out of the Default state in the enumeration phase and into the
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In addition to configuration registers, the USB registers also provide status information. The USB registers control/status bits are referred to where appropriate in the following sections while section 13.15.11 on page 175 gives a full description of all USB registers. 13.15.2 48 MHz Clock A 48 MHz external crystal must be used for the USB Controller to operate correctly. This 48 MHz clock is divided by two internally to generate the system clock at 24 MHz. It is important that the crystal oscillator is stable before the USB Controller is accessed. See 13.10.3 for details on how to set up the crystal oscillator. 13.15.3 USB Enable The USB Controller must be enabled before it is used. This is performed by setting the SLEEP.USB_EN bit to 1. Setting SLEEP.USB_EN to 0 will reset the USB Controller. 13.15.4 USB Interrupts There are 3 interrupt flag registers with associated interrupt enable mask registers. The USBCIF register contains flags for common USB interrupts. The USBIIF register has interrupt flags for endpoint 0 and all the IN endpoints. USBOIF has interrupt flags for all OUT endpoints. All interrupts except SOF and and SUSPEND are initially enabled after reset. When the interrupt flag of an enabled interrupt is set, the USB interrupt is asserted. This interrupts the 8051 CPU which will start executing the interrupt service routine if there is no higher priority interrupts pending. The USB Controller uses interrupt number 6 for USB interrupts. This is the same interrupt number used for Port 2 inputs. Thus, the
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Addressed state. All configured endpoints will then be available for the application. The EP0 FIFO is only used as IN or OUT at a time. The maximum packet size for endpoint 0 is fixed at 32 bytes. Double buffering is not provided for endpoint 0. Endpoint 0 is controlled through the USBCS0 register. The USBINDEX register must be set to 0. The USBCNT0 register contains the number of bytes received. 13.15.5.1 Interrupts Endpoint 0 will generate an interrupt on any of the following events: * * A data packet has been received. A data packet that was loaded into the EP0 FIFO has been sent to the USB host. An IN transaction completed. has been bit The firmware can also terminate the current transaction by setting the USBCS0.SEND_STALL bit. The USB Controller will then send STALL handshake in response to requests from the USB host. When firmware receives an EP0 interrupt and finds that the USBCS0.SENT_STALL bit is set it should clear the USBCS0.SENT_STALL bit and abort the current transfer. If EP0 receives an unexpected token during the Data stage USBCS0.SETUP_END will be set and an EP0 interrupt will be generated. EP0 will then switch to the IDLE state. Firmware should then set the USBCS0.CLR_SETUP_END bit and abort the current transfer. If USBCS0.OUTPKT_RDY is set, this indicates that another SETUP packet has been received that firmware should process. 13.15.5.3 SETUP state) Transactions (IDLE
* * *
The USBCS0.SENT_STALL has been set.
The USBCS0.SETUP_END bit has been set.
13.15.5.2 Error conditions When a protocol error occurs the USB Controller sends a STALL handshake. The USBCS0.SENT_STALL bit is set and an interrupt is generated. A protocol error can be any of the following: * An OUT token is received after USBCS0.DATA_END has been set to complete the OUT Data stage. Thus, the host tries to send more data than expected. An IN token is received after USBCS0.DATA_END has been set to complete the IN Data stage. Thus, the host tries to receive more data than expected. The USB host tries to send a packet that exceeds the maximum packet size during the OUT Data stage. The size of the DATA1 packet received during the Status stage is not 0.
*
The first transaction in a control transfer consists of a SETUP packet, sent from the host. A SETUP packet is always 8 bytes and contains a pre-defined set of fields. This is the Setup stage of a control transfer and EP0 will be in the IDLE state. Consult the USB 2.0 Specification [2] for details about this. The USB Controller will reject the first packet if the size of the packet is not 8 bytes. Also, the USB Controller will examine the contents of the SETUP packet to determine whether the Data stage will consist of IN or OUT transactions and EP 0 will switch state to TX or RX when the USBCS0.CLR_OUTPKT_RDY bit is set if USBCS0.DATA_END is not set. When a packet is received, the USBCS0.OUTPKT_RDY bit will be set and an EP0 interrupt is generated. Firmware should perform the follwing when a SETUP packet has been received: 1. Unload the SETUP packet from the EP0 FIFO 2. Examine the contents and perform the appropriate operations
*
*
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3. Set the USBCS0.CLR_OUTPKT_RDY bit. This denotes the end of the Setup stage. If the control transfer has no Data stage, the USBCS0.DATA_END bit must also be set. If there is no Data stage, the USB Controller will stay in the IDLE state. 13.15.5.4 IN Transactions (TX state) If the control transfer requires data to be sent to the host, the Setup Stage will be followed by one or more IN transactions (a Data IN stage). In this case the USB Controller will be in TX state and only accept IN tokens. If more than 32 bytes (maximum packet size) is to be sent, the data must be split into a number of 32 byte packets followed by a residual packet. If the number of bytes to send is divisible by 32, the residual packet will be a zero length data packet. Thus, a packet size less than 32 bytes denotes the end of the transfer. Firmware should load the EP0 FIFO with the first data packet and set the USBCS0.INPKT_RDY bit as soon as possible after the USBCS0.CLR_OUTPKT_RDY bit has been set. The USBCS0.INPKT_RDY bit will be cleared and an EP0 interrupt will be generated when the data packet has been sent. Firmware might then load more data packets as necessary. An EP0 interrupt will be generated for each packet sent. Firmware must set USBCS0.DATA_END in addition to USBCS0.INPKT_RDY when the last data packet has been loaded. This will start the Status stage of the control transfer. EP0 will switch to the IDLE state when the Status stage has completed. The Status stage may fail if the USBCS0.SEND_STALL bit is set. The USBCS0.SENT_STALL bit will then be set and an interrupt will be generated as explained in section 13.15.5.2. If USBCS0.INPKT_RDY is not set when receiving an IN token, the USB Controller will reply with a NAK to indicate that the endpoint is working, but temporarily has no data to send. 13.15.5.5 OUT Transactions (RX state) If the control transfer requires data to be received from the host, the Setup stage will be followed by one or more OUT transactions (a Data OUT stage). In this case the USB Controller will be in RX state and only accept OUT tokens. If more than 32 bytes (maximum packet size) is to be received, the data must be split into a number of 32 byte packets followed by a residual packet. If the number of bytes is divisible by 32, the residual packet will be a zero length data packet. Thus, a packet size less than 32 bytes denotes the end of the transfer. The USBCS0.OUTPKT_RDY bit will be set and an EP0 interrupt will be generated when a data packet has been received. The firmware should set USBCS0.CLR_OUTPKT_RDY when the data packet has been unloaded from the EP0 FIFO. When the last data packet has been received (packet size less than 32) firmware should also set USBCS0.DATA_END. This will start the Status stage of the control transfer. EP0 will switch to the IDLE state when the Status stage has completed. The Status stage may fail if the DATA1 packet received is not a zero length data packet or the USBCS0.SEND_STALL bit is set. The USBCS0.SENT_STALL bit will then be set and an interrupt will be generated as explained in section 13.15.5.2. 13.15.6 Endpoints 1 - 5 Each endpoint can be used as a IN only, OUT only or IN/OUT. For a IN/OUT endpoint there are basically two endpoints, a IN and a OUT endpoint assiociated with the endpoint number. Configuration and control of IN endpoints is performed by accessing the USBCSIL and USBCSIH registers. The USBCSOL and USBCSOH registers are used to configure and control OUT endpoints. Each IN and OUT endpoint can be configured as a Isochronous or Bulk/Interrupt endpoint. This is done by setting the USBCSIH.ISO and USBCSOH.ISO bits. Bulk and Interrupt endpoints are handled identically by the USB Controller but will have different properties from a firmware perspective.
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The USBINDEX register must have the value of the endpoint number before the Indexed Endpoint Registers are accessed. 13.15.6.1 FIFO Management Each endpoint has a number of FIFO memory bytes available for incoming and outgoing data packets. Table 50 shows the FIFO size for endpoints 1 - 5. It is the firmware that is responsible for setting the USBMAXI and USBMAXO registers correctly for each endpoint so that no data potentially gets overwritten. When both the IN and OUT endpoint of an endpoint number do not use double buffering, the sum of USBMAXI and USBMAXO must not exceed the FIFO size for the endpoint. Figure 36 a) shows how the IN and OUT FIFO memory for an endpoint is organized with single buffering. The IN FIFO grows down from the top of the endpoint memory region while the
EP Number 1 2 3 4 5
OUT FIFO grows up from the bottom of the endpoint memory region. When the IN or OUT endpoint of an endpoint number use double buffering, the sum of USBMAXI and USBMAXO must not exceed half the FIFO size for the endpoint. Figure 36 b) illustrates the IN and OUT FIFO memory for an endpoint that uses double buffering. Notice that the second OUT buffer starts from the middle of the memory region and grows upwards. The second IN buffer also starts from the middle of the memory region but grows downwards. To configure an endpoint as IN only, set USBMAXO to 0 and to configure an endpoint as OUT only, set USBMAXI to 0. The USBMAXO and USBMAXI registers should be 0 for unused endpoints.
FIFO Size (in bytes) 32 64 128 256 512
Table 50 FIFO Sizes for EP 1 - 5
Figure 36: IN/OUT FIFOs, a) Double buffering b) Single buffering
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13.15.6.2 Double buffering Double buffering allows two packets to be buffered in the FIFO. This reduces retransmission and is highly recommended for isochronous endpoints which do not use retransmission. For isochronous endpoint one data packet will be sent/received every USB frame. However, the data packet may be sent/received at any time during the USB frame period. Thus, two data packets may be sent/received at a few micro seconds interval. For isochronous endpoints an incoming packet will be lost if there is no buffer available and a zero length data packet will be sent if there is no data packet ready for transmission when the USB host requests data. Double buffering is not as critical for bulk and interrupt endpoints since packets will not be lost. Double buffering, however, may improve the effective data rate for bulk endpoints. To enable double buffering for an IN endpoint, set USBCSIH.IN_DBL_BUF to 1. To enable double buffering for an OUT endpoint, set USBCSOH.OUT_DBL_BUF to 1. 13.15.6.3 FIFO Access The endpoint FIFOs are accessed by reading and writing to the registers in Table 53. Writing to a register causes the byte written to be inserted into the IN FIFO. Reading a register causes the next byte in the OUT FIFO to be extracted and the value of this byte to be returned. When a data packet has been written to a IN FIFO the USBCSIL.INPKT_RDY bit must be set. If double buffering is enabled, the USBCSIL.INPKT_RDY bit will be cleared immediately after it has been written and another data packet can be loaded. This will not generate an interrupt, since an interrupt is only generated when a packet has been sent. When double buffering is used firmware should check the status of the USBCSIL.PKT_PRESENT bit before writing to the IN FIFO. If this bit is 0, two data packets can be written. Double buffered isochronous endpoints should only need to load two packets the first time the IN FIFO is loaded. After that, one packet is loaded for every USB frame. To send a zero length data packet set USBCSIL.INPKT_RDY without loading a data packet into the IN FIFO. A data packet can be read from the OUT FIFO when the USBCSOL.OUTPKT_RDY bit is set. An interrupt will be generated when this occurs, if enabled. The size of the data packet is kept in the USBCNTH:USBCNTL registers. When the data packet has been read from the OUT FIFO, the USBCSOL.OUTPKT_RDY bit must be cleared. If double buffering is enabled there may be two data packets in the FIFO. If another data packet is ready when the USBCSOL.OUTPKT_RDY bit is cleared the USBCSOL.OUTPKT_RDY bit will be set immediately and an interrupt will be generated to signal that a new data packet has been received. The USBCSOL.FIFO_FULL bit will be set when there are two data packets in the OUT FIFO. The AutoClear feature is supported for OUT endpoints. When enabled, the USBCSOL.OUTPKT_RDY bit is cleared automatically when USBMAXO bytes have been read from the OUT FIFO. The AutoClear feature is enabled by setting the USBCSOH.AUTOCLEAR bit. The AutoClear feature can be used to reduce the time the data packet occupies the OUT FIFO buffer and is typically used for bulk endpoints. A complementary AutoSet feature is also supported for IN endpoints. When enabled, the USBCSIL.INPKT_RDY bit is set automatically when USBMAXI bytes have been written to the IN FIFO. The AutoSet feature is enabled by setting the USBCSOH.AUTOSET bit. The AutoSet feature can reduce the overall time it takes to send a data packet and is typically used for bulk endpoints. 13.15.6.4 Endpoint Interrupts IN endpoints generate interrupts by setting the interrupt flags in the USBIIF register in the following situations: * * * A data packet has been successfully sent to the host. A STALL condition has been generated by the hardware. The IN FIFO is flushed due to the USBCSIH.FLUSH_PACKET bit being set.
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OUT endpoints generate interrupts by setting the interrupt flags in the USBOIF register in the following situations: * A data packet has been received. USBCSOL.OUTPKT_RDY has been set. A STALL condition has been generated by the hardware. will be set and an interrupt will be generated. Double buffering requires the data packet to be loaded during the frame before the packet is sent. If the first data packet is loaded before an IN token is received the data packet will be sent during the same frame the packet is loaded which violates the double buffering strategy. Thus, when double buffering is used, the USBPOW.ISO_WAIT_SOF bit should be set to avoid this. Setting this bit will ensure that a loaded data packet is not sent until the next SOF token has been received. The AutoSet feature will typically not be used for isochronous endpoints since the packet size will increase or decrease from frame to frame to match the source data rate. Notice that an isochronous cannot be stalled. endpoint
*
13.15.6.5 Bulk/Interrupt IN Endpoint Interrupt IN transfers occur at regular intervals while bulk IN transfers utilize available bandwidth not allocated to isochronous, interrupt and control transfers and can happen at any time. Interrupt IN endpoints may set the USBCSIH.FRC_DATA_TOG bit. When this bit is set the data toggle bit is continuously toggled regardless of whether an ACK was received. This feature is typically used by interrupt IN endpoints that report rate feedback for isochronous endpoints. A Bulk/Interrupt IN endpoint can be stalled by setting the USBCSIL.SEND_STALL bit to 1. When the endpoint is stalled the USB Controller will respond with a STALL handshake to IN tokens. The USBCSIL.SENT_STALL bit will then be set and an interrupt will be generated. A bulk transfer longer than the maximum packet size is performed by splitting the transfer into a number of data packets of maximum size followed by a smaller data packet containing the remaining bytes. If the transfer length is divisible by the maximum packet size a zero length data packet is sent last. Thus, a packet with a size less than the maximum packet size denotes the end of the transfer. The AutoSet feature can be useful in this case, since many data packets will be of maximum size. 13.15.6.6 Isochronous IN Endpoint An isochronous IN endpoint is guaranteed to be able to send exactly one data packet every USB frame and is typically used to send a continous stream of data. If there is no data packet loaded in the IN FIFO when the USB host requests data, the USB Controller sends a zero length data packet. The USBCSIL.UNDERRUN bit
13.15.6.7 Bulk/Interrupt OUT Endpoint Interrupt OUT transfers occur at regular intervals while bulk OUT transfers utilize available bandwidth not allocated to isochronous, interrupt and control transfers and can happen at any time. A Bulk/Interrupt OUT endpoint can be stalled by setting the USBCSOL.SEND_STALL bit to 1. When the endpoint is stalled the USB Controller will respond with a STALL handshake when the host is done sending the data packet. The data packet is discarded and is not placed in the OUT FIFO. The USB Controller will set the USBCSOL.SENT_STALL bit and generate an interrupt when the STALL handshake is sent. As the AutoSet feature is useful for bulk IN endpoints, the AutoClear feature is useful for OUT endpoint since many packets will be of maximum size. 13.15.6.8 Isochronous OUT Endpoint An isochronous OUT endpoint is guaranteed to receive exactly one data packet every USB frame and is typically used to receive a continous stream of data. If there is no buffer available when a data packet is being received the
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USBCSOL.OVERRUN is set and the packet data will be lost. Firmware can reduce the chance for this to happen by using double buffering and use DMA to effectively unload data packets. An isochronous data packet in the OUT FIFO may have bit errors. The hardware will detect this condition and set USBCSOL.DATA_ERROR. Firmware should therefore always check this bit when unloading a data packet. The AutoClear feature will typically not be used for isochronous endpoints since the packet size will increase or decrease from frame to frame to match the source data rate. Notice that an isochronous cannot be stalled. 13.15.7 DMA DMA should be used to fill the IN endpoint FIFOs and empty the OUT endpoint FIFOs. Using DMA will improve read/write performance significantly compared to using the 8051 CPU. It is therefore highly recommended to use DMA unless timing is not critical or only a few bytes are to be transferred. There are no DMA triggers for the USB Controller. Thus, DMA transfers must be
MSB LSB
triggered by firmware. The DMA Transfer Mode should be set to block transfer. The word size can be byte (8 bits) or word (16 bits). When word size transfer is used the ENDIAN register must be set correctly. The ENDIAN.USBRLE bit selects whether word data is read as little or big endian from OUT FIFOs and the ENDIAN.USBWLE bit selects whether word data is written as little or big endian to IN FIFOs. Writing and reading words for the different settings is shown in Figure 37 and Figure 38 respectively. Notice that the setting for these bits will be used for all endpoints. Consequently, it is not possible to have multiple DMA channels active at once that use different endianness. The ENDIAN register must be configured to use big endian for both read and write for a word size transfer to produce the same result as a byte size transfer of an even number of bytes. Refer to section 12.12 for more information about the ENDIAN register. Word size transfer is slightly more efficient than byte transfer. Refer to section 13.2 for more information about how to use DMA.
endpoint
To Host
SYNC
PID
MSB
LSB
MSB
LSB
MSB
LSB
CRC16
EOP
MSB
LSB
To Host
SYNC
PID
LSB
MSB
LSB
MSB
LSB
MSB
CRC16
EOP
Figure 37 Writing Little/Big Endian
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Figure 38 Reading Little/Big Endian While in suspend mode, only limited current can be sourced from the USB bus. See the USB 2.0 Specification [2] for details about this. To be able to meet the suspend current requirement, the CC2511Fx should be taken down to PM1 when suspend is detected. The CC2511Fx should not enter PM2 or PM3 since this will reset the USB Controller. Any valid non-idle signaling on the USB bus will cause the USB Resume Interrupt to be generated and wake up the system if the USB Resume Interrupt is configured correctly. Refer to 13.15.4.1 for details about how to set up the USB Resume Interrupt. When the system wakes up (enters PM0) from suspend no USB registers must be accessed before XOSC has stabilized. Be aware that the USB Controller will stay in suspend mode until XOSC has stabilized and non-idle signaling is detected on the USB bus. The USBCIF.RESUMEIF interrupt flag will be set and a USB Interrupt will be generated if enabled when the USB Controller exits from suspend mode. USB Reset will also wake up the system from suspend. The USB Resume Interrupt will be generated, but the USBCIF.RSTIF interrupt flag will be set instead of the USBCIF.RESUMEIF interrupt flag. 13.15.10 Remote Wakeup
13.15.8 USB Reset A USB hub may signal reset at any time. When reset signaling is detected on the bus, the USB Controller will set USBCIF.RSTIF and generate an interrupt if USBCIE.RSTIE is set. The firmware should take appropriate action when a USB Reset occurs. A USB Reset would normally cause the system to be initialized to a known reset state. The USB function will typically be reset one or more times during the enumeration phase right after the USB cable is connected. A USB Reset places the device in the default state. In this state the device will only respond to address 0 (the default address). The following actions are performed by the USB Controller when a USB Reset occurs: * * * * * * USBADDR is set to 0 USBINDEX is set to 0 All endpoint FIFOs are flushed E0CSR, USBCSIL, USBCSIH, USBCSOL, USBCSOH are cleared. All interrupts, except suspend, are enabled An interrupt is generated
Thus, firmware should close all pipes and wait for a new enumeration phase when USB Reset is detected. 13.15.9 Suspend and Resume The USB Controller will enter suspend mode when the USB bus has been continuously idle for 3 ms. An interrupt will be generated if the USBCIE.SUSPENDIE is set.
The USB Controller can resume from suspend by signaling resume to the USB hub. Resume is performed by setting USBPOW.RESUME to 1 for approximately 10 ms. According to the USB 2.0 Specification, the resume signaling must be present for at least 1 ms and no more
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than 15 ms. It is, however, recommended to keep the resume signaling for approximately 10 ms. Notice that the device must report back to the USB host that it supports Remote Wakeup when the host sends the GET_STATUS Standard Device Request. 13.15.11 USB Registers into three groups: The Common USB Registers, The Indexed Endpoint Registers and the Endpoint FIFO Registers. Overview of Common USB Registers. Table 51, Table 52 and Table 53 give an overview of register addresses for each of the three groups respectively while the remaining tables in this section describe each register. The Indexed Endpoint Registers represent the currently selected endpoint. The USBINDEX register is used to select the endpoint. Notice that the upper register addresses 0xDE2C - 0xDE3F are reserved.
This section describes all USB registers used for control and status for the USB. The USB registers reside in XDATA memory space in the region 0xDE000xDE3F. These registers can be divided
XDATA Address 0xDE00 0xDE01 0xDE02 0xDE03 0xDE04 0xDE05 0xDE06 0xDE07 0xDE08 0xDE09 0xDE0A 0xDE0B 0xDE0C 0xDE0D 0xDE0E Register USBADDR USBPOW USBIIF USBOIF USBCIF USBIIE USBOIE USBCIE USBFRML USBFRMH USBINDEX Description Function Address Power/Control Register IN Endpoints and EP0 Interrupt Flags Reserved OUT Endpoints Interrupt Flags Reserved Common USB Interrupt Flags IN Endpoints and EP0 Interrupt Enable Mask Reserved Out Endpoints Interrupt Enable Mask Reserved Common USB Interrupt Enable Mask Current Frame Number (Low byte) Current Frame Number (High byte) Selects current endpoint. Make sure this register has the value of the endpoint before any of the registers in Table 52 are accessed. This register must be set to a value in the range 0 - 5.
Table 51 Overview of Common USB Registers
XDATA Address 0xDE10 0xDE11 0xDE12 0xDE13 0xDE14 0xDE15 0xDE16 0xDE17 Register USBMAXI USBCS0 USBCSIL USBCSIH USBMAXO USBCSOL USBCSOH USBCNT0 USBCNTL USBCNTH Description Max. packet size for IN endpoint EP0 Control and Status (USBINDEX = 0) IN EP{1-5} Control and Status Low IN EP{1-5} Control and Status High Max. packet size for OUT endpoint OUT EP{1-5} Control and Status Low OUT EP{1-5} Control and Status High Number of received bytes in EP0 FIFO (USBINDEX = 0) Number of bytes in OUT FIFO Low Number of bytes in OUT FIFO High
Valid USBINDEX value(s) 1-5 0 1-5 1-5 1-5 1-5 1-5 0 1-5 1-5
Table 52 Overview of Indexed Endpoint Registers
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XDATA Address 0xDE20 0xDE22 0xDE24 0xDE26 0xDE28 0xDE2A Register USBF0 USBF1 USBF2 USBF3 USBF4 USBF5 Description Endpoint 0 FIFO Endpoint 1 FIFO Endpoint 2 FIFO Endpoint 3 FIFO Endpoint 4 FIFO Endpoint 5 FIFO
Table 53 Overview of Endpoint FIFO Registers
0xDE00: USBADDR - Function Address
Bit 7 6:0 Field Name UPDATE USBADDR[6:0] Reset 0 0x00 R/W R0 R/W Description This bit is set when the USBADDR register is written and cleared when the address becomes effective. Function address.
0xDE01: USBPOW - Power/Control Register
Bit 7 Field Name ISO_WAIT_SOF Reset 0 R/W R/W Description When this bit is set the USB Controller will only send zero length data packets from the time INPKTRDY is set and until the first SOF token has been received. This only applies to isochronous endpoints. Unused During reset signaling, this bit is set. Drive resume signaling for remote wakeup. According to the USB Specification the duration of driving resume must be at least 1 ms and no more than 15 ms. It is recommended to keep this bit set for approximately 10 ms. This bit must not be set until the USB Controller has been in suspend mode for at least 2 ms. Suspend Mode entered. This bit will only be used when SUSPEND_EN is set. Reading the USBCIF register or setting RESUME will clear this bit. Suspend Detection Enable. When this bit is set, the USBCIF.SUSPEND will be set when the USB bus has been idle for 3 ms. An interrupt will also be generated, if USBCIE.SUSPEND is set.
6:4 3 2
RST RESUME
000 0 0
R0 R R/W
1
SUSPEND
0
R
0
SUSPEND_EN
0
R/W
0xDE02: USBIIF - IN Endpoints and EP0 Interrupt Flags
Bit 7:6 5 Field Name INEP5IF Reset 00 0 R/W R0 R Description Unused Interrupt flag for IN endpoint 5 Page 176 of
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Bit 4 3 2 1 0 Field Name INEP4IF INEP3IF INEP2IF INEP1IF EP0IF Reset 0 0 0 0 0 R/W R R R R R Description Interrupt flag for IN endpoint 4 Interrupt flag for IN endpoint 3 Interrupt flag for IN endpoint 2 Interrupt flag for IN endpoint 1 Interrupt flag for endpoint 0
0xDE04: USBOIF - Out Endpoints Interrupt Flags
Bit 7:6 5 4 3 2 1 0 Field Name OUTEP5IF OUTEP4IF OUTEP3IF OUTEP2IF OUTEP1IF Reset 00 0 0 0 0 0 0 R/W R0 R R R R R R0 Description Unused Interrupt flag for OUT endpoint 5 Interrupt flag for OUT endpoint 4 Interrupt flag for OUT endpoint 3 Interrupt flag for OUT endpoint 2 Interrupt flag for OUT endpoint 1 Unused
0xDE06: USBCIF - Common USB Interrupt Flags
Bit 7:4 3 2 1 0 Field Name SOFIF RSTIF RESUMIF SUSPENDIF Reset 0000 0 0 0 0 R/W R0 R R R R Description Unused Start-Of-Frame interrupt flag Reset interrupt flag Resume interrupt flag Suspend interrupt flag
0xDE07: USBIIE - IN Endpoints and EP0 Interrupt Enable Mask
Bit 7:6 5 4 3 2 1 0 Field Name INEP5IE INEP4IE INEP3IE INEP2IE INEP1IE EP0IE Reset 00 1 1 1 1 1 1 R/W R0 R/W R/W R/W R/W R/W R/W Description Unused IN endpoint 5 interrupt enable IN endpoint 4 interrupt enable IN endpoint 3 interrupt enable IN endpoint 2 interrupt enable IN endpoint 1 interrupt enable Endpoint 0 interrupt enable
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0xDE09: USBOIE - Out Endpoints Interrupt Enable Mask
Bit 7:6 5 4 3 2 1 0 Field Name OUTEP5IE OUTEP4IE OUTEP3IE OUTEP2IE OUTEP1IE Reset 00 1 1 1 1 1 0 R/W R0 R/W R/W R/W R/W R/W R0 Description Unused OUT endpoint 5 interrupt enable OUT endpoint 4 interrupt enable OUT endpoint 3 interrupt enable OUT endpoint 2 interrupt enable OUT endpoint 1 interrupt enable Unused
0xDE0B: USBCIE - Common USB Interrupt Enable Mask
Bit 7:4 3 2 1 0 Field Name SOFIE RSTIE RESUMEIE SUSPENDIE Reset 0000 0 1 1 0 R/W R0 R/W R/W R/W R/W Description Unused Start-Of-Frame interrupt enable Reset interrupt enable Resume interrupt enable Suspend interrupt enable
0xDE0C: USBFRML - Current Frame Number (Low byte)
Bit 7:0 Field Name FRAME[7:0] Reset 0x00 R/W R Description Low byte of 11-bit frame number
0xDE0D: USBFRMH - Current Frame Number (High byte)
Bit 7:3 2:0 Field Name FRAME[10:8] Reset 00000 000 R/W R0 R Description Always 0 High byte of 11-bit frame number
0xDE0E: USBINDEX - Current Endpoint Index Register
Bit 7:4 3:0 Field Name USBINDEX[3:0] Reset 0000 0000 R/W R0 R/W Description Always 0 Endpoint selected. Must be set to value in the range 0 - 5.
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0xDE10: USBMAXI - Max. packet size for IN endpoint
Bit 7:0 Field Name USBMAXI[7:0] Reset 0x00 R/W R/W Description Maximum packet size in units of 8 bytes for IN endpoint selected by USBINDEX register. The value of this register should correspond to the wMaxPacketSize field in the Standard Endpoint Descriptor for the endpoint. This register must not be set to a value grater than the available FIFO memory for the endpoint.
0xDE11: USBCS0 - EP0 Control and Status (USBINDEX = 0)
Bit 7 Field Name CLR_SETUP_END Reset 0 R/W R/W H0 6 CLR_OUTPKT_RDY 0 R/W H0 5 SEND_STALL 0 R/W H0 4 SETUP_END 0 R Description Set this bit to clear the SETUP_END bit. It will be cleared automatically. Set this bit to clear the OUTPKT_RDY bit. It will be cleared automatically. Set this bit to make the USB Controller reply with a STALL during the next transfer. This bit is automatically cleared. Used to terminate the current transaction. This bit is set if the control transfer ends due to a premature end of control transfer. The FIFO will be flushed and the interrupt flag USBIIF.EP0IF will be set. Set the CLR_SETUP_END bit to clear this bit. This bit is used to signal the end of a data transfer. This bit must be set in the following three situations: * * * When the last data packet has been loaded and INPKT_RDY is set When the last data packet has been unloaded and CLR_OUTPKT_RDY is set When INPKT_RDY is set without having loaded the FIFO (for sending a zero length data packet).
3
DATA_END
0
R/W H0
The USB Controller will clear this bit automatically. 2 SENT_STALL 0 R/W H1 1 INPKT_RDY 0 R/W H0 This bit is set when a STALL has been sent. The interrupt flag USBIIF.EP0 will be set. This bit must be cleared from firmware. Set this bit when a data packet has been loaded into the EP0 FIFO to notify the USB Controller that a new data packet is ready to be transferred. When the data packet has been sent, this bit is cleared and the interrupt flag is set. Data packet received. This bit is set when an incoming data packet has been placed in the OUT FIFO. Set the CLR_OUTPKT_RDY bit to clear this bit. The interrupt flag is also set when this bit is set.
0
OUTPKT_RDY
0
R
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0xDE11: USBCSIL - IN EP{1-5} Control and Status Low
Bit 7 Field Name Reset 0 R/W R0 Description Unused
6
CLR_DATA_TOG
0
R/W H0
Setting this bit will reset the data toggle to 0. Thus, setting this bit will force the next data packet to be a DATA0 packet. This bit is automatically cleared. This bit is set when a STALL has been sent. The FIFO will be flushed and the INPKT_RDY bit is set to 0. This bit must be cleared from firmware. Set this bit to make the USB Controller reply with a STALL handshake when receiving IN tokens. Firmware must clear this bit to end the stall condition. It is not possible to stall an isochronous endpoint, thus this bit will only have effect if the IN endpoint is configured as bulk/interrupt. Flush next packet that is ready for transfer. The INPKT_RDY bit will be cleared. If there are two packets in the IN FIFO due to double buffering, this bit must be set twice to completely flush the IN FIFO. This bit is automatically cleared. This bit is set when INPKT_RDY has not been set when an IN token is received. A zero length data packet is transmitted in response to the IN token. This bit is only used for isochronous endpoints. Firmware should clear this bit. This bit is set when there is at least one packet in the IN FIFO. Set this bit when a data packet has been loaded into the IN FIFO to notify the USB Controller that a new data packet is ready to be transferred. When the data packet has been sent, this bit is cleared and the interrupt flag is set.
5
SENT_STALL
0
R/W
4
SEND_STALL
0
R/W
3
FLUSH_PACKET
0
R/W H0
2
UNDERRUN
0
R/W
1 0
PKT_PRESENT INPKT_RDY
0 0
R R/W H0
0xDE12: USBCSIH - IN EP{1-5} Control and Status High
Bit 7 Field Name AUTOSET Reset 0 R/W R/W Description When this bit is set, the INPKT_RDY bit is automatically set when a data packet of maximum size (specified by USBMAXI) has been loaded into the IN FIFO. Selects IN endpoint type. 0 - Bulk/Interrupt 1 - Isochronous 5:4 3 FORCE_DATA_TOG 10 0 R R/W Unused Setting this bit will force the IN endpoint data toggle to switch and the data packet to be flushed from the IN FIFO even though an ACK was received. This feature can be useful when reporting rate feedback for isochronous endpoints. Unused Set this bit to enable double buffering of data packets.
6
ISO
0
R/W
2:1 0
IN_DBL_BUF
0 0
R0 R/W
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0xDE13: USBMAXO - Max. packet size for OUT endpoint
Bit 7:0 Field Name USBMAXO[7:0] Reset 0x00 R/W R/W Description Maximum packet size in units of 8 bytes for OUT endpoint selected by USBINDEX register. The value of this register should correspond to the wMaxPacketSize field in the Standard Endpoint Descriptor for the endpoint. This register must not be set to a value grater than the available FIFO memory for the endpoint.
0xDE14: USBCSOL - OUT EP{1-5} Control and Status Low
Bit 7 Field Name CLR_DATA_TOG Reset 0 R/W R/W H0 6 5 SENT_STALL SEND_STALL 0 0 R/W R/W Description Setting this bit will reset the data toggle to 0. Thus, setting this bit will force the next data packet to be a DATA0 packet. This bit is automatically cleared. This bit is set when a STALL has been sent. This bit must be cleared from firmware. Set this bit to make the USB Controller reply with a STALL handshake. Firmware must clear this bit to end the stall condition. It is not possible to stall an isochronous endpoint, thus this bit will only have effect if the OUT endpoint is configured as bulk/interrupt. Flush next packet that is to be read from the OUT FIFO. If there are two packets in the IN FIFO due to double buffering, this bit must be set twice to completely flush the IN FIFO. This bit is automatically cleared. This bit is set if there is a CRC or bit-stuff error in the packet received. Cleared when OUTPKT_RDY is cleared. This bit will only be valid if the OUT endpoint type is isochronous. Bulk/Interrupt endpoints use retransmission when errors occur while there is no retransmission for isochronous endpoints. This bit is set when an OUT packet cannot be loaded into the OUT FIFO and the OUT endpoint type is isochronous. Firmware should clear this bit. OUT FIFO full. No more packets can be loaded. This bit is set when a packet has been successfully received and is ready to be read from OUT FIFO. This bit should be cleared as soon as the packet has been unloaded from the FIFO. The interrupt flag for the OUT endpoint is set when this bit is set.
4
FLUSH_PACKET
0
R/W H0
3
DATA_ERROR
0
R
2
OVERRUN
0
R/W
1 0
FIFO_FULL OUTPKT_RDY
0 0
R R/W
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0xDE15: USBCSOH - OUT EP{1-5} Control and Status High
Bit 7 Field Name AUTOCLEAR Reset 0 R/W R/W Description When this bit is set, the OUTPKT_RDY bit is automatically cleared when a data packet of maximum size (specified by USBMAXO) has been unloaded into the OUT FIFO. Selects OUT endpoint type. 0 - Bulk/Interrupt 1 - Isochronous 5:4 3:1 0 OUT_DBL_BUF 00 000 0 R/W R0 R/W Unused. Must be 0. Unused Set this bit to enable double buffering of data packets.
6
ISO
0
R/W
0xDE16: USBCNT0 - Number of received bytes in EP0 FIFO (USBINDEX = 0)
Bit 7:6 5:0 Field Name USBCNT0[5:0] Reset 00 0x00 R/W R0 R Description Unused. Number of received bytes into EP 0 FIFO. Only valid when OUTPKT_RDY is set.
0xDE16: USBCNTL - Number of bytes in OUT FIFO Low
Bit 7:0 Field Name USBCNT[7:0] Reset 0x00 R/W R Description Number of received bytes into OUT FIFO selected by USBINDEX register. Only valid when OUTPKT_RDY is set.
0xDE17: USBCNTH - Number of bytes in OUT FIFO High
Bit 7:3 2:0 Field Name USBCNT[10:8] Reset 0x00 0x00 R/W R0 R Description Unused Number of received bytes into OUT FIFO selected by USBINDEX register. Only valid when OUTPKT_RDY is set.
0xDE20: USBF0 - Endpoint 0 FIFO
Bit 7:0 Field Name USBF0[7:0] Reset 0x00 R/W R/W Description Endpoint 0 FIFO register. Reading this register causes one byte to be extracted from the EP0 FIFO. The value of the extracted value is returned. Writing to this register inserts one byte with the value written into the EP0 FIFO. Note: The FIFO memory for EP0 is used for both incoming and outgoing data packets.
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0xDE22: USBF1 - Endpoint 1 FIFO
Bit 7:0 Field Name USBF1[7:0] Reset 0x00 R/W R/W Description Endpoint 1 FIFO register. Reading this register causes one byte to be extracted from the EP1 OUT FIFO. The value of the extracted value is returned. Writing to this register inserts one byte with the value written into the EP1 IN FIFO.
0xDE24: USBF2 - Endpoint 2 FIFO
Bit 7:0 Field Name USBF2[7:0] Reset 0x00 R/W R/W Description Endpoint 2 FIFO register. Reading this register causes one byte to be extracted from the EP2 OUT FIFO. The value of the extracted value is returned. Writing to this register inserts one byte with the value written into the EP2 IN FIFO.
0xDE26: USBF3 - Endpoint 3 FIFO
Bit 7:0 Field Name USBF3[7:0] Reset 0x00 R/W R/W Description Endpoint 3 FIFO register. Reading this register causes one byte to be extracted from the EP3 OUT FIFO. The value of the extracted value is returned. Writing to this register inserts one byte with the value written into the EP3 IN FIFO.
0xDE28: USBF4 - Endpoint 4 FIFO
Bit 7:0 Field Name USBF4[7:0] Reset 0x00 R/W R/W Description Endpoint 4 FIFO register. Reading this register causes one byte to be extracted from the EP4 OUT FIFO. The value of the extracted value is returned. Writing to this register inserts one byte with the value written into the EP4 IN FIFO.
0xDE2A: USBF5 - Endpoint 5 FIFO
Bit 7:0 Field Name USBF5[7:0] Reset 0x00 R/W R/W Description Endpoint 5 FIFO register. Reading this register causes one byte to be extracted from the EP5 OUT FIFO. The value of the extracted value is returned. Writing to this register inserts one byte with the value written into the EP5 IN FIFO.
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13.16 Flash Controller The CC2510FX/CC2511Fx contains 8, 16 or 32 KB flash memory for storage of program code. The flash memory is programmable from the user software. The Flash Controller handles writing and erasing the embedded flash memory. The flash memory consists of 8, 16 or 32 pages of 1024 bytes each, depending on the total flash size. The flash memory is byte-addressable from the CPU and 16-bit word-programmable. The flash controller has the following features: * * * * * 16-bit word programmable Page erase Lock bits for write-protection and code security Flash erase timing 20 ms Flash write timing 20 s programmable, meaning data is written as 16-bit words. Therefore the actual writing to flash memory takes place each time two bytes have been written to FWDATA. The CPU will not be able to access the flash, e.g. to read program code, while a flash write operation is in progress. Therefore the program code executing the flash write must be executed from RAM, meaning that the program code must reside in the area 0xF000 to 0xFF00 in XDATA/CODE memory space. When a flash write operation is executed from RAM, the CPU continues to execute code from the next instruction after the write to FWDATA, which initiated the flash write operation. The FCTL.SWBSY bit must be 0 before accessing the flash after a flash write, otherwise an access violation occurs. This also means that FCTL.SWBSY must be 0 before program execution can continue at a location in flash memory. 13.16.1.1 DMA Flash Write When using DMA write operations, the data to be written into flash is stored in DATA/XDATA memory. A DMA channel is configured to read the data to be written from memory and write this data to the Flash Write Data register, FWDATA with the DMA trigger event FL enabled. Thus the Flash Controller will trigger a DMA transfer when the Flash Write Data register, FWDATA, is ready to receive new data. The DMA channel should be configured to perform a block to fixed, single mode, byte size transfers. When the DMA channel is armed, starting a flash write will trigger the first DMA transfer. Figure 39 shows an example how a DMA channel is configured and how a DMA transfer is initiated to write a block of data from a location in XDATA to flash memory.
13.16.1 Flash Write Data is written to the flash memory by using a program command initiated by writing the Flash Control register, FCTL. Flash write operations can program any number of locations in the flash memory at a time - it is however important to make sure the pages to be written are erased first. A write operation is performed using one out of two methods; * * Through DMA transfer Through CPU SFR access.
The DMA transfer method is the preferred way to write to the flash memory. A write operation is initiated by writing a 1 to FCTL.WRITE. The address to start writing at, is given by FADDRH:FADDRL. During each single write operation FCTL.SWBSY is set high. During a write operation the data written to the FWDATA register is forwarded to the flash memory. The flash memory is 16-bit word-
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Setup DMA channel: SRCADDR= DESTADDRR=FWDATA VLEN=0 LEN= WORDSIZE=byte TMODE=single mode TRIG=FL SRCINC=yes DESTINC=no IRQMASK=yes M8=0 PRIORITY=high
Setup flash address
Arm DMA Channel
Start flash write
; Write a consecutive block of data from XDATA to consecutive locations in ; flash memory using DMA ; Assumes 26 MHz system clock is used ; MOV DPTR,#DMACFG ;load data pointer with address for DMA ;channel configuration and ;start writing DMA configuration MOV A,#SRC_HI ;source data high address MOVX @DPTR,A ; INC DPTR ; MOV A,#SRC_LO ;source data low address MOVX @DPTR,A ; INC DPTR ; MOV A,#0DFh ;destination high address = HIGH(X_FWDATA) MOVX @DPTR,A ; INC DPTR ; MOV A,#0AFh ;destination low address = LOW(X_FWDATA) MOVX @DPTR,A ; INC DPTR ; MOV A,#BLK_LEN ;block length MOVX @DPTR,A ; INC DPTR ; MOV A,#012h ;8 bits, single mode, use FL trigger MOVX @DPTR,A ; INC DPTR ; MOV A,#042h ;increment source by 1, don't increment MOVX @DPTR,A ;destination, mask interrupt, high DMA ;priority MOV DMA0CFGL,#DMACFG_LO ;setup start address for current DMA MOV DMA0CFGH,#DMACFG_HI ;configuration MOV DMAARM,#01h ;arm DMA channel 0 MOV FADDRH,#00h ;setup flash address high MOV FADDRL,#01h ;setup flash address low MOV FWT,#2Ah ;setup flash timing MOV FCTL,#02h ;start flash page write => trigger DMA . .
Figure 39: Flash write using DMA
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13.16.1.2 CPU Flash Write The CPU can also write directly to the flash. The CPU writes data to the Flash Write Data register, FWDATA. The flash memory is written each time two bytes have been written to FWDATA. The CPU can poll the FCTL.SWBSY status to determine when the flash is ready for two more bytes to be written to FWDATA.. Performing flash write from XDATA The steps required to start a flash write operation from XDATA are shown in Figure 40 on page 186.
Disable interrupts
YES
BUSY=1?
Setup FCTL, FWT, FADDRH, FADDRL
Write FWDATA
; Write 32-bit word from XDATA ; Assumes 26 MHz system clock is ; CLR EA C1: MOV A,FCTL JB ACC.7,C1 MOV FADDRH,#00h MOV FADDRL,#01h MOV FWT,#2Ah MOV FCTL,#02h MOV FWDATA,#12h MOV FWDATA,#34h
used ;mask interrupts ;wait until flash controller is ready ;setup flash address high ;setup flash address low ;setup flash timing ;set flash page write ;first byte ;second byte, initiates write
Figure 40 : Flash write performed from XDATA 13.16.2 Flash Page Erase A page erase is initiated by setting FCTL.ERASE to 1. The page addressed by FADDRH[6:1] is erased when a page erase is initiated. Note that if a page erase is initiated simultaneously with a page write, i.e. FCTL.WRITE is set to 1, the page erase will be performed before the page write operation. The FCTL.BUSY bit can be polled to see when the page erase has completed.
252
Note: if flash erase operations are performed from within flash memory and the watchdog timer is enabled, a watchdog timer interval must be selected that is longer than 20 ms, the duration of the flash erase operation, so that the CPU will manage to clear the watchdog timer. Performing flash erase from flash memory.
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The steps required to perform a flash page erase from within flash memory are outlined in Figure 41. Note that, while executing program code from within flash memory, when a flash
; Erase page ; Assumes 26 ; CLR C1: MOV JB MOV MOV MOV MOV RET in flash memory MHz system clock is used EA A,FCTL ACC.7,C1 FADDRH,#00h FADDRL,#01h FWT,#2Ah FCTL,#01h ;mask interrupts ;wait until flash controller is ready ;setup flash address high ;setup flash address low ;setup flash timing ;erase page ;continues here when flash is ready
erase or write operation is initiated, program execution will resume from the next instruction when the flash controller has completed the operation.
Figure 41: Flash page erase performed from flash memory
13.16.3 Flash Lock Protection For software protection purposes a set of lock protection bits can be written once after each chip erase has been performed. The lock protect bits can only be written through the Debug Interface. There are three kinds of lock protect bits as described in this section. The flash lock bits reside at location 0x000 in the Flash Information page as described in section 12.11. The LSIZE[2:0] lock protect bits are used to define a section of the flash memory which is write protected. The size of the write protected area can be set by the LSIZE[2:0] lock protect bits in sizes of eight steps from 0 to 32 KB. Notice that the only supported value for LSIZE[2:0] is 0 and 7 for CC2510F8, CC2511F8, CC2510F16 and CC2511F16. The second type of lock protect bits is BBLOCK, which is used to lock the boot sector page (page 0 ranging from address 0 to 0x03FF). When BBLOCK is set to 0, the boot sector page is locked. The third type of lock protect bit is DBGLOCK, which is used to disable hardware debug support through the Debug Interface. When DBGLOCK is set to 0, all debug commands are disabled. The lock protect bits are written as a normal flash write to FWDATA, but the Debug Interface needs to select the Flash Information Page first instead of the Flash Main Page which is the default setting. The Information Page is selected through the Debug Configuration which is written through the Debug Interface only. Refer to section 12.9 on page 60 for details on how to select the Flash Information Page using the Debug Interface. Table 54 defines the byte containing the flash lock protection bits. Note that this is not an SFR register, but instead the byte stored at location 0x000 in Flash Information Page.
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Table 54: Flash Lock Protection Bits Definition
Bit 7:5 4 Name Description Reserved, write as 0 Boot Block Lock 0 1 3:1 Page 0 is write protected Page 0 is writeable, unless LSIZE is 000
BBLOCK
LSIZE[2:0]
Lock Size. Sets the size of the upper Flash area which is write protected. Byte sizes are listed below 000 001 010 011 100 101 110 111 32K bytes (All pages) 24K bytes 16K bytes 8K bytes 4K bytes 2K bytes 1K bytes (CC2510F32 and CC2511F32 only) (CC2510F32 and CC2511F32 only) (CC2510F32 and CC2511F32 only) (CC2510F32 and CC2511F32 only) (CC2510F32 and CC2511F32 only) (CC2510F32 and CC2511F32 only)
0 bytes (no pages)
0
DBGLOCK
Debug lock bit 0 1 Disable debug commands Enable debug commands
13.16.4 Flash Write Timing The Flash Controller contains a timing generator which controls the timing sequence of flash write and erase operations. The timing generator uses the information set in the Flash Write Timing register, FWT.FWT[5:0], to set the internal timing. FWT.FWT[5:0] must be set to a value according to the currently selected system clock frequency. The value set in the FWT.FWT[5:0] shall be set according to the system clock frequency by the following equation.
FWT =
21000 F 16 * 10 9
Where F is the system clock frequency. The initial value held in FWT.FWT[5:0] after a reset is 0x11 which corresponds to 13 MHz CPU clock frequency (High speed RC oscillator). The FWT values for the possible system clock frequencies are given in Table 55.
System clock frequency (MHz) 13 16 24 26
FWT 0x11 0x15 0x20 0x23
Table 55: Flash timing (FWT) values 13.16.5 Flash Controller Registers The Flash Controller described in this section. registers are
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FCTL (0xAE) - Flash Control
Bit 7 6 5 4 Name Reset 0 0 0 R/W R/W R R R/W 0 Description Indicates that write or erase is in operation Indicates that single write is busy; avoid writing to FWDATA register while this is true Not used. Continuous read enable mode 0 1 Avoid wasting power; turn on read enables to flash only when needed Enable continuous read enables to flash when read is to be done. Reduces internal switching of read enables, but greatly increases power consumption.
BUSY SWBSY CONTRD
3:2 1
0
R/W R0/W
Not used. Page Write. Start writing page given by FADDRH:FADDRL. If ERASE is set to 1, a page erase is performed before the write. Page Erase. Erase page that is given by FADDRH:FADDRL
WRITE ERASE
0
0
0
R0/W
FWDATA (0xAF) - Flash Write Data
Bit 7:0 Name Reset 0x00 R/W R/W Description Flash write data. Data written to FWDATA is written to flash when
FWDATA[7:0]
FCTL.WRITE is set to 1. FADDRH (0xAD) - Flash Address High Byte
Bit 7:6 5:0 Name Reset 00 0x00 R/W R/W R/W Description Not used High byte of flash address Bits 5:1 will select page to access, while bit 0 is MSB of row access.
FADDRH[6:0]
FADDRL (0xAC) - Flash Address Low Byte
Bit 7:0 Name Reset 0x00 R/W R/W Description Low byte of flash address Bit 0 of FADDRH and bits 7:6 will select which row to write to, while bits 5:0 will select which location to write to.
FADDRL[7:0]
FWT (0xAB) - Flash Write Timing
Bit 7:6 5:0 Name Reset 00 0x25 R/W R/W R/W Description Not used Flash Write Timing. Controls flash timing generator.
FWT[5:0]
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14 Crystal Oscillator
14.1 CC2510FX Crystal Oscillator A crystal in the frequency range 26 MHz27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C201 and C211) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals should equal CL for the crystal to oscillate at the specified frequency. The crystal oscillator is amplitude regulated. This means that a high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4 Vpp signal swing. This ensures a fast start-up, and keeps the drive level to a minimum. The ESR of the crystal should be within the specification in order to ensure a reliable start-up (see section Table 9 on page 15). 14.2 CC2511Fx Crystal Oscillator The CC2511Fx requires a 48 MHz frequency crystal to be used. If a fundamental crystal is used, only the loading capacitor values need to be changed compared to the CC2510FX crystal oscillator. If a 3rd overtone crystal is used, an additional inductor and capacitor is needed. Figure 9 shows this configuration. Values for capacitors and the inductor are given in Table 27.
CL =
1 1 1 + C211 C201
+ C parasitic
The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasitic capacitance is typically 2.5 pF. The crystal oscillator circuit is shown in Figure 7. Typical component values for different values of CL are given in Table 9.
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15 Radio
RADIO CONTROL DEMODULATOR
ADC
LNA
PACKET HANDLER
RF_P RF_N
0 90
FREQ SYNTH MODULATOR
PA
Figure 42: CC2510FX/CC2511Fx Radio Module A simplified block diagram of the radio module in the CC2510FX/CC2511Fx is shown in Figure 42. and Q LO signals to the down-conversion mixers in receive mode. The 26/48 MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part. An SFR register interface is used for data buffer access from the CPU. Configuration and status registers are accessed through registers mapped to XDATA memory. The digital baseband includes support for channel configuration, packet handling and data buffering. An on-chip voltage regulator delivers a regulated 1.8 V supply voltage.
CC2510FX/CC2511Fx
features a low-IF receiver. The received RF signal is amplified by the low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitized by the ADCs. Automatic gain control (AGC), fine channel filtering, demodulation bit/packet synchronization is performed digitally.
The transmitter part of CC2510FX/CC2511Fx is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase shifter for generating the I 15.1 Command strobes The CPU uses a set of command strobes to control operation of the radio in
CC2510FX/CC2511Fx.
Command strobes may be viewed as single byte instructions which each control some function of the radio. These command strobes must be used to enable
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CPU INTERFACE
ADC
FEC / INTERLEAVER
CC2510FX / CC2511Fx
the frequency synthesizer, enable receive mode, enable transmit mode and other functions. The command strobes are issued by writing to the RFST SFR register. The list of all strobe commands which are defined is given in Table 56.
SIDLE
Default state when the radio is not receiving or transmitting. Typ. current consumption in radio: 1.8mA.
SCAL Used for calibrating frequency synthesizer upfront (entering receive or transmit mode can Manual freq. then be done quicker). synth. calibration Transitional state. Typ. current consumption in radio: 7.6mA.
Idle
SRX or STX or SFSTXON
Frequency synthesizer is on, ready to start transmitting. Transmission starts very quickly after receiving the STX command strobe.Typ. current consumption in radio: 7.6mA.
SFSTXON
Frequency synthesizer startup, optional calibration, settling
Frequency synthesizer is turned on, can optionally be calibrated, and then settles to the correct frequency. Transitional state. Typ. current consumption in radio: 7.6mA.
Frequency synthesizer on
STX SRX STX TXOFF_MODE=01 SFSTXON or RXOFF_MODE=01
Typ. current consumption in radio: 11.5mA at -12dBm output, 15.4mA at -6dBm output, 21.6mA at 0dBm output.
Transmit mode
STX or RXOFF_MODE=10 SRX or TXOFF_MODE=11
Receive mode
Typ. current consumption: from 13.3mA (strong input signal) to 15.6mA (weak input sgnal).
TXOFF_MODE=00
RXOFF_MODE=00
Optional transitional state. Typ. current consumption: 7.6mA. Optional freq. synth. calibration
Idle
Figure 43: Simplified state diagram, with typical usage and current consumption in radio
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RFST Value 0x00 Command Strobe Name SFSTXON Description
Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). While in RX / TX issuing this command strobe will force the radio to go to a wait state where only the synthesizer is running (for quick RX / TX turnaround). Calibrate frequency synthesizer and turn it off (enables quick start). Enable RX. Perform calibration first if coming from IDLE and
0x01 0x02 0x03 0x04 0x05 all others
SCAL SRX STX SIDLE SAFC SNOP
MCSM0.FS_AUTOCAL=1.
In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: Only go to TX if channel is clear. Exit RX / TX, turn off frequency synthesizer. Perform AFC adjustment of the frequency synthesizer No operation.
Table 56: Command strobes The RF interrupt can also be used to trigger a timer capture in Timer 1. The RF interrupt flags are described in the next section. 15.3.1 Interrupt registers Two of the main interrupt control SFR registers are used to enable the RF and RFTXRX interrupts. These are the following: * * RFTXRX RF : IEN0. RFTXRXIE : IEN2.RFIE
15.2 Radio Registers The operation of the radio is configured through a set of RF registers. These RF registers are mapped to XDATA memory space as shown in Figure 10 on page 36. In addition to configuration registers, the RF registers also provide status information from the radio. The RF registers control/status bits are referred to where appropriate in the following sections while section 15.18 on page 216 gives a full description of all RF registers. 15.3 Interrupts The radio is associated with two interrupt vectors on the CPU. These are the RFTXRX interrupt (interrupt 0) and the RFIF interrupt (interrupt 12) with the following functions * * RFTXRX: complete RF: flags RX data ready or TX data all other RFIF interrupt
Two main interrupt flag SFR registers hold the RF and RFERR interrupt flags. These are the following: * * RFTXRX RF : TCON. RFTXRX : S1CON.RFIF
Refer to section 12.7 for details about the interrupts. The RF interrupt is the combined interrupt from six different sources in the radio. Two SFR registers are used for setting the six individual RFIF radio interrupt flags and interrupt enables. These are the RFIF and RFIM registers. The interrupt flags in SFR register RFIF show the status for each interrupt source for the RF interrupt vector. The interrupt enable bits in RFIM are used to disable individual interrupt sources for the RF interrupt vector. Note that masking
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The RF interrupt vector combines the interrupts in RFIF shown on page 194. Note that these RF interrupts are risingedge triggered. Thus an interrupt is generated when e.g. the SFD status flag goes from 0 to 1.
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an interrupt source in RFIM does not affect the update of the status in the RFIF register. Due to the use of the individual interrupt masks in RFIM, and the main interrupt mask for the RF interrupt given by IEN2.RFIE there is two-layered masking of this interrupt. Special attention needs to be taken when processing this type of interrupt as described below. To clear the RF interrupt, S1CON.RFIF and the interrupt flag in RFIF need to be cleared. The order and method of doing this is shown in Figure 44. Note that S1CON is cleared after RFIF, otherwise S1CON.RFIF could be set once again due to the same interrupt.
MOV MOV MOV
RFIF,#00h S1CON,#00h RFIM,RFIM
;clear all interrupt flags ;clear main interrupt flags ;set interrupt mask
Figure 44: Clearing RF Interrupt
RFIF (0xE9) - RF Interrupt Flags
Bit 7 Name IRQ_TXUNF Reset 0 R/W R/W0 Description TX underflow. 0 1 6 IRQ_RXOVF 0 R/W0 No interrupt pending Interrupt pending
RX overflow. 0 1 No interrupt pending Interrupt pending
5
IRQ_TIMEOUT
0
R/W0
RX timeout, no packet has been received in the programmed period. 0 1 No interrupt pending Interrupt pending
4
IRQ_DONE
0
R/W0
Packet received/transmitted. Also used to detect underflow/overflow conditions. 0 1 No interrupt pending Interrupt pending
3
IRQ_CS
0
R/W0
Carrier sense. 0 1 No interrupt pending Interrupt pending
2
IRQ_PQT
0
R/W0
Preamble quality reached. 0 1 No interrupt pending Interrupt pending
1
IRQ_CCA
0
R/W0
Clear Channel Assessment 0 1 No interrupt pending Interrupt pending
0
IRQ_SFD
0
R/W0
Start of Frame Delimiter, sync word detected 0 1 No interrupt pending Interrupt pending
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RFIM (0x91) - RF Interrupt Mask
Bit 7 Name Reset 0 R/W R/W Description TX underflow. 0 1 6 Interrupt disabled Interrupt enabled
IM_TXUNF
IM_RXOVF
0
R/W
RX overflow. 0 1 Interrupt disabled Interrupt enabled
5
IM_TIMEOUT
0
R/W
RX timeout, no packet has been received in the programmed period. 0 1 Interrupt disabled Interrupt enabled
4
IM_DONE
0
R/W
Packet received/transmitted. Also used to detect underflow/overflow conditions. 0 1 Interrupt disabled Interrupt enabled
3
IM_CS
0
R/W
Carrier sense. 0 1 Interrupt disabled Interrupt enabled
2
IM_PQT
0
R/W
Preamble quality reached. 0 1 Interrupt disabled Interrupt enabled
1
IM_CCA
0
R/W
Clear Channel Assessment 0 1 Interrupt disabled Interrupt enabled
0
IM_SFD
0
R/W
Start of Frame Delimiter, sync word detected 0 1 Interrupt disabled Interrupt enabled
15.4 TX/RX Data Transfer Transmit data is written to the radio when writing to the RF Data register, RFD. Received data is returned when the RFD register is read. It is required that the user software uses FIFO structures in memory to implement RX and TX FIFOs. In most cases it is recommended that the transfer of data between FIFOs in memory and the RF Data register, RFD, involves the use of DMA channels with RFD as source/destination and DMA trigger RADIO. For description on the usage of DMA, refer to section 13.2 on page 84. A simple example of writing TX data to the radio is shown in Figure 45. This example does not use DMA, but illustrates some of the basic principles.
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; Start radio TX ; simple example, assumes required frequency, modulation format and ; data rate has been set in RF registers ; MOV DPTR,PA_TABLE0 ;setting PA output power MOV A,#0FFh ; MOVX @DPTR,A ; MOV CLKCON,#00H ;select 26 MHz XOSC MOV RFST,#03H ;start TX with STX command strobe C1: JNB IE0,C1 ;wait for interrupt flag telling radio is CLR IE0 ;ready to accept data, then write MOV RFD,#02H ;first data to radio, packet length=2 C2: JNB IE0,C2 ;wait for radio CLR IE0 ; MOV RFD,#12H ;send first byte in payload C3: JNB IE0,C3 ;wait for radio CLR IE0 ; MOV RFD,#34H ;send second byte in payload ;done
Figure 45: Simple RF transmit example
15.5 Data Rate Programming The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency.
R DATA 2 20 DRATE _ E = log 2 f XOSC R DATA 2 28 - 256 DRATE _ M = f XOSC 2 DRATE _ E
If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M=0. The data rate can be set from 1.2 kbps to 500 kbps with the minimum step size as shown in Table 57.
RDATA =
(256 + DRATE _ M ) 2 DRATE _ E f
228
XOSC
The following approach can be used to find suitable values for a given data rate:
Data rate start 0.8 kbps 3.17 kbps 6.35 kbps 12.7 kbps 25.4 kbps 50.8 kbps 101.6 kbps 203.1 kbps 406.3 kbps
Typical data rate 1.2 / 2.4 kbps 4.8 kbps 9.6 kbps 19.6 kbps 38.4 kbps 76.8 kbps 153.6 kbps 250 kbps 500 kbps
Data rate stop 3.17 kbps 6.35 kbps 12.7 kbps 25.4 kbps 50.8 kbps 101.6 kbps 203.1 kbps 406.3 kbps 500 kbps
Data rate step size 0.0062 kbps 0.0124 kbps 0.0248 kbps 0.0496 kbps 0.0992 kbps 0.1984 kbps 0.3967 kbps 0.7935 kbps 1.5869 kbps
Table 57: Data rate step size
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15.6 Receiver Channel Filter Bandwidth In order to meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filter bandwidth, which scales with the crystal oscillator frequency. The following formula gives the relation between the register settings and the channel filter bandwidth:
BWchannel =
f XOSC 8 (4 + CHANBW _ M )*2CHANBW _ E
The CC2510FX/CC2511Fx supports channel filter bandwidths shown in Table 58.
MDMCFG4. CHANBW_M 00 01 10 11
MDMCFG4.CHANBW_E 00 812 650 541 464 01 406 325 270 232 10 203 162 135 116 11 102 81 68 58
Table 58: Channel filter bandwidths [kHz] (26 MHz crystal)
For best performance, the channel filter bandwidth should be selected so that the signal bandwidth occupies at most 80% of the channel filter bandwidth. The channel centre tolerance due to crystal accuracy should also be subtracted from the signal bandwidth. The following example illustrates this: With the channel filter bandwidth set to 600 kHz, the signal should stay within 80%
of 600 kHz, which is 480 kHz. Assuming 2.44 GHz frequency and 20 ppm frequency uncertainty for both the transmitting device and the receiving device, the total frequency uncertainty is 40 ppm of 2.44 GHz, which is 98 kHz. If the whole transmitted signal bandwidth is to be received within 480 kHz, the transmitted signal bandwidth should be maximum 480 kHz-2*98 kHz, which is 284 kHz.
15.7 Demodulator, Symbol Synchronizer and Data Decision
CC2510FX/CC2511Fx contains an advanced
and highly configurable demodulator. Channel filtering and frequency offset compensation is performed digitally. To generate the RSSI level (see section 15.10.3 for more information) the signal level in the channel is estimated. Data filtering is also included for enhanced performance. 15.7.1 Frequency Offset Compensation When using FSK or MSK modulation, the demodulator will compensate for the offset between the transmitter and receiver frequency, within certain limits, by estimating the centre of the received data.
This value is available in the FREQEST status register. By issuing the SAFC command strobe, the measured offset, FREQEST.FREQOFF_EST, can automatically be used to adjust the frequency offset programming in the frequency synthesizer. This will add the current RX frequency offset estimate to the value in FSCTRL0.FREQOFF, which adjust the synthesizer frequency. Thus, the frequency offset will be compensated in both RX and TX when the SAFC command strobe is used.
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To avoid compensating for frequency offsets measured without a valid signal in the RF channel, FREQEST.FREQOFF_EST is copied to an internal register when issuing the SAFC strobe in RX, and when a sync word is detected. If SAFC was issued in RX, this internal value is added to FSCTRL0.FREQOFF after exiting RX. Issuing SAFC when not in RX will immediately add the internal register value to FSCTRL0.FREQOFF. Thus, the SAFC strobe should be issued when currently receiving a packet, or outside the RX state. Note that frequency offset compensation is not supported for OOK modulation. 15.7.2 Bit Synchronization The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 15.5 on page 196. Resynchronization is performed continuously to adjust for error in the incoming symbol rate. 15.7.3 Byte synchronization Byte synchronization is achieved by a 15.8 Packet Handling Hardware Support The CC2510FX/CC2511Fx has built-in hardware support for packet oriented radio protocols. In transmit mode, the packet handler will add the following elements to the packet stored to be transmitted: * * * * A programmable number of preamble bytes. Four preamble bytes are recommended. A two byte Synchronization Word. Can be duplicated to give a 4-byte sync word. (Recommended). Optionally whiten the data with a PN9 sequence. Optionally Interleave and Forward Error Code the data.
Bit 7:0 Field name RSSI
continuous sync word search. The sync word is a 16 or 32 bit configurable field that is automatically inserted at the start of the packet by the modulator in transmit mode. The demodulator uses this field to find the byte boundaries in the stream of bits. The sync word will also function as a system identifier, since only packets with the correct predefined sync word will be received. The sync word detector correlates against the user-configured 16bit sync word. The correlation threshold can be set to 15/16 bits match or 16/16 bits match. The sync word can be further qualified using the preamble quality indicator mechanism described below and/or a carrier sense condition. The sync word is programmed with SYNC1 and SYNC0. In order to make false detections of sync words less likely, a mechanism called preamble quality indication (PQI) can be used to qualify the sync word. A threshold value for the preamble quality must be exceeded in order for a detected sync word to be accepted. See section 15.10.2 on page 203 for more details.
*
Optionally compute and add a CRC checksum over the data field.
In receive mode, the packet handling support will de-construct the data packet: * * * * * Preamble detection. Sync word detection. Optional one byte address check. Optionally compute and check CRC. Optionally append two status bytes (see Table 59 and Table 60) with RSSI value, Link Quality Indication and CRC status.
Description RSSI value
Table 59: Received packet status byte 1 (first byte appended after the data)
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CC2510FX / CC2511Fx
Bit 7
Field name CRC_OK
Description 1: CRC for received data OK (or CRC disabled) 0: CRC error in received data
6:0
LQI
The Link Quality Indicator estimates how easily a received signal can be demodulated
Table 60: Received packet status byte 2 (second byte appended after the data) Note that register fields that control the packet handling features should only be altered when CC2510FX/CC2511Fx is in the IDLE state. 15.8.1 Data whitening From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the control loops in the receiver uniform operation conditions (no data dependencies). Real world data often contain long sequences of zeros and ones. Performance can then be improved by whitening the data before transmitting, and de-whitening in the receiver. With CC2510FX/CC2511Fx, this can be done automatically by setting PKTCTRL0.WHITE_DATA=1. All data, except the preamble and the sync word, are then XOR-ed with a 9-bit pseudorandom (PN9) sequence before being transmitted. At the receiver end, the data are XOR-ed with the same pseudo-random sequence. This way, the whitening is reversed, and the original data appear in the receiver. Setting PKTCTRL0.WHITE_DATA=1 is recommended for all uses, except when over-the-air compatibility with other systems is needed. 15.8.2 Packet format The format of the data packet can be configured and consists of the following items: * * * * * * Preamble Synchronization word Length byte or constant programmable packet length Optional Address byte Payload Optional 2 byte CRC
Optional data whitening Optionally FEC encoded/decoded Optional CRC-16 calculation Address field Length field Sync word CRC-16
Legend: Inserted automatically in TX, processed and removed in RX. Optional user-provided fields processed in TX, processed but not removed in RX. Unprocessed user data (apart from FEC and/or whitening)
Preamble bits (1010...1010)
Data field
8 x n bits
16/32 bits
8 bits
8 bits
8 x n bits
16 bits
Figure 46: Packet Format
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The preamble pattern is an alternating sequence of ones and zeros (01010101...). The minimum length of the preamble is programmable. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the modulator will send the sync word and then data from the RFD register. The number of preamble bytes is programmed with the MDMCFG1.NUM_PREAMBLE value. The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte sync word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by using MDMCFG2.SYNC_MODE=3 or 7. The sync word will then be repeated twice. Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet length is set by the PKTLEN register. In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and the optional automatic CRC. The PKTLEN register is used to set the maximum packet length allowed in RX. Any packet received with a length byte with a value greater than PKTLEN will be discarded. With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission and reception will continue until turned off manually. The infinite mode can be turned off while a packet is being transmitted or received. As described in the next section, this can be used to support packet formats with different length configuration than natively supported by CC2510FX/CC2511Fx.
CC2510FX/CC2511Fx supports
both fixed packet length protocols and variable length protocols. The maximum packet length is 255 bytes. For longer packets, infinite packet length mode must be used.
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15.8.2.1 Arbitrary length field configuration The fixed length field can be reprogrammed during receive and transmit. This opens the possibility to have a different length field configuration than supported for variable length packets. At the start of reception, the packet length is set to a large value. The CPU reads out enough bytes to interpret the length field in the packet. Then the PKTLEN value is set according to this value. The end of packet will occur when the byte counter in the packet handler is equal to the PKTLEN register. Thus, the CPU must be able to program the correct length, before the internal counter reaches the packet length. By utilizing the infinite packet length option, arbitrary packet length is available. At the start of the packet, the infinite mode must be active. On the TX side, the PKTLEN register is set to mod(length, 256). On the RX side the MCU reads out enough bytes to interpret the length field in the packet and sets the PKTLEN register to mod(length, 256). When less than 256 bytes remains of the packet the MCU disables infinite packet length and activates fixed length packets. When the internal byte counter reaches the PKTLEN value, the transmission or reception ends. Automatic CRC appending/checking can be used (by setting PKTCTRL0.CRC_EN to 1) When for example a 600-byte packet is to be transmitted, the MCU should do the following (see also Figure 47): * * * * * Set PKTCTRL0.LENGTH_CONFIG=2 (10). Pre-program the PKTLEN register to mod(600,256)=88. Transmit at least 345 bytes. Set PKTCTRL0.LENGTH_CONFIG=0 (00). The transmission ends when the packet counter reaches 88. A total of 600 bytes are transmitted.
Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again 0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,.......................
Infinite packet length enabled
Fixed packet length enabled when less than 256 bytes remains of packet
600 bytes transmitted and received
Length field transmitted and received. Rx and Tx PKTLEN value set to mod(600,256) = 88
Figure 47: Arbitary length field configuration
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15.8.3 Packet filtering in Receive Mode from RFD and the result is sent as two extra bytes at the end of the payload data. If whitening is enabled, the length byte, payload data and the two CRC bytes will be whitened. This is done before the optional FEC/Interleaver stage. Whitening is enabled by setting PKTCTRL0.WHITE_DATA=1. If FEC/Interleaving is enabled, the length byte, payload data and the two CRC bytes will be scrambled by the interleaver, and FEC encoded before being modulated. 15.8.5 Packet Handling in Receive Mode In receive mode, the demodulator and packet handler will search for a valid preamble and the sync word. When found, the demodulator has obtained both bit and byte synchronism and will receive the first payload byte. If FEC/Interleaving is enabled, the FEC decoder will start to decode the first payload byte. The interleaver will de-scramble the bits before any other processing is done to the data. If whitening is enabled, the data will be dewhitened at this stage. When variable packet length is enabled, the first byte is the length byte. The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. If fixed packet length is used, the packet handler will accept the programmed number of bytes. Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler computes CRC and matches it with the appended CRC checksum. At the end of the payload, the packet handler will optionally write two extra packet status bytes that contain CRC status, link quality indication and RSSI value. 15.9 Modulation Formats
CC2510FX/CC2511Fx
supports two different packet-filtering criteria: address filtering and maximum length filtering. 15.8.3.1 Address Filtering
Setting PKTCTRL1.ADR_CHK to any other value than zero enables the packet address filter. The packet handler engine will compare the destination address byte in the packet with the programmed node address in the ADDR register and the 0x00 broadcast address when PKTCTRL1.ADR_CHK=10 or both 0x00 and 0xFF broadcast addresses when PKTCTRL1.ADR_CHK=11. If the received address matches a valid address, the packet is accepted and a RFTXRX interrupt and a DMA trigger is generated. If the address match fails, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting). If the received address matches a valid address when the packet length is set to infinite and address filtering is enabled, the first byte read from the radio will be 0xFF, followed by the address byte and then the payload data. 15.8.3.2 Maximum Length Filtering In the variable packet length mode the PKTLEN.PACKET_LENGTH register value is used to set the maximum allowed packet length. If the received length byte has a larger value than this, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting). 15.8.4 Packet Handling in Transmit Mode The payload that is to be transmitted must be written into RFD. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If fixed packet length is enabled, then the first byte written to RFD is interpreted as the destination address, if this feature is enabled in the device that receives the packet. The modulator will first send the programmed number of preamble bytes. If data is written to RFD, the modulator will send the two-byte (optionally 4-byte) sync word and then the payload written to RFD. If CRC is enabled, the checksum is calculated over all the data pulled
CC2510FX/CC2511Fx
supports amplitude, frequency and phase shift modulation formats. The desired modulation format is set in the MDMCFG2.MOD_FORMAT register. Optionally, the data stream can be Manchester coded by the modulator and decoded by the demodulator. This option is enabled by setting MDMCFG2.MANCHESTER_EN=1. Manchester
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encoding is not supported at the same time as using the FEC/Interleaver option. 15.9.1 Frequency Shift Keying 2-FSK can optionally be shaped by a Gaussian filter with BT=1, producing a GFSK modulated signal. The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by: 15.9.3 Amplitude Modulation The supported amplitude modulation On-Off Keying (OOK) simply turns on or off the PA to modulate 1 and 0 respectively. 15.10 Received Signal Qualifiers and Link Quality Information
CC2510FX/CC2511Fx has several qualifiers that
can be used to increase the likelihood that a valid sync word is detected. 15.10.1 Sync Word Qualifier If sync word detection in RX is enabled in register MDMCFG2 the CC2510FX/CC2511Fx will not start writing received data to the RFD register and perform the packet filtering described in section 15.8.3 before a valid sync word has been detected. The sync word qualifier mode is set by MDMCFG2.SYNC_MODE and is summarized in Table 62. Carrier sense in Table 62 is described in section 15.10.4
f dev
f = xosc (8 + DEVIATION _ M ) 2 DEVIATION _ E 217
The symbol encoding is shown in Table 61.
Format 2FSK/GFSK
Symbol `0' `1'
Coding - Deviation + Deviation
Table 61: Symbol encoding for FSK modulation
MDMCFG2. Sync word qualifier mode
15.9.2 Minimum Shift Keying When using MSK , the complete transmission (preamble, sync word and payload) will be MSK modulated. Phase shifts are performed with a constant transition time. The fraction of a symbol period used to change the phase can be modified with the DEVIATN.DEVIATION_M setting. This is equivalent to changing the shaping of the symbol.
6
SYNC_MODE 000 001 010 011 100 101 110 111 No preamble/sync 15/16 sync word bits detected 16/16 sync word bits detected 30/32 sync word bits detected No preamble/sync, carrier sense above threshold 15/16 + carrier sense above threshold 16/16 + carrier sense above threshold 30/32 + carrier sense above threshold
CC2510FX/CC2511Fx inverts the sync word and
data compared to e.g. signal generators.
6
The MSK modulation format implemented in
Table 62: Sync word qualifier mode 15.10.2 Preamble Quality Threshold (PQT) The Preamble Quality Threshold (PQT) syncword qualifier adds the requirement that the received sync word must be preceded with a preamble with a quality above the programmed threshold. and decreases the counter by 4 each time a bit is received that is the same as the last bit. The counter saturates at 0 and 31. The threshold is configured with the register field PKTCTRL1.PQT. A threshold of 4*PQT for this counter is used to gate sync word detection.
Identical to offset QPSK with half-sine shaping (data coding may differ)
Another use of the preamble quality threshold is as a qualifier for the optional RX termination timer. See section 15.12.3 on page 210 for details. The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit,
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By setting the value to zero, the preamble quality qualifier of the sync word is disabled. A "Preamble Quality reached" flag can also be observed in the status register bit PKTSTATUS.PQT_REACHED. This flag asserts when the received signal exceeds the PQT. 15.10.3 RSSI The RSSI value is an estimate of the signal level in the chosen channel. This value is based on the current gain setting in the RX chain and the measured signal level in the channel. In RX mode, the RSSI value can be read continuously from the RSSI status register. The RSSI value is in dB with 1/2dB resolution. The RSSI update rate depends on the receiver filter bandwidth (BWchannel defined in Section Error! Reference source not found.) and AGCCTRL0.FILTER_LENGTH. If PKTCTRL1.APPEND_STATUS is enabled the last RSSI value of the packet is automatically added to the first byte appended after the data. The RSSI value read from the RSSI status register is a 2's complement number. The following procedure can be used to convert the RSSI reading to an absolute power level (RSSI_dBm). 1) Read the RSSI status register 2) Convert the reading from a hexadecimal number to a decimal number (RSSI_dec) 3) If RSSI_dec 128 then RSSI_dBm = (RSSI_dec - 256)/2 - RSSI_offset 4) Else if RSSI_dec < 128 then RSSI_dBm = (RSSI_dec)/2 - RSSI_offset Error! Reference source not found.Table 63 gives typical values for the RSSI_offset. Figure 48 shows typical plots of RSSI reading as a function of input power level for different data rates.
f RSSI =
2 BWchannel 8 2 FILTER _ LENGTH
Data rate 2.4 kbps 10 kbps 250 kbps 500 kbps
RSSI_offset (decimal) 71 69 72 72
Table 63: Typical RSSI_offset values
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0.0 -10.0 -20.0 -30.0 RSSI readout [dBm] -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 -110.0 -120.0 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
Input pow er [dBm] 2.4 kbps 10 kbps 250 kbps 250 kbps, reduced current 500 kbps
Figure 48: Typical RSSI value vs. input power level for some typical data rates
15.10.4 Carrier Sense (CS) The Carrier Sense flag is used as a sync word qualifier and for CCA. The CS flag can be set based on two conditions, which can be individually adjusted: * CS is asserted when the RSSI is above a programmable absolute threshold, and de-asserted when RSSI is below the same threshold (with hysteresis). CS is asserted when the RSSI has increased with a programmable number of dB from one RSSI sample to the next, and de-asserted when RSSI has decreased with the same number of dB. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with time varying noise floor. on page 206) and the optional fast RX termination (see section See section 15.12.3 on page 210 for details.). CS can be used to avoid interference from e.g. WLAN. 15.10.5 CS Absolute Threshold The absolute threshold related to the RSSI value is given by:
THRRSSI = MAGN _ TARGET + CARRIER _ SENSE _ ABS _ THR - GAIN MAX
*
Carrier Sense (CS) can be used as a sync word qualifier that requires the signal level to be higher than the threshold for a sync word search to be performed. The signal can also be observed in the status register bit PKTSTATUS.CS. Other uses of Carrier Sense include the TX-If-CCA function (see section 15.10.7
The maximum possible gain can be reduced using the AGCCTRL2.MAX_LNA_GAIN and AGCCTRL2.MAX_DVGA_GAIN register fields. CARRIER_SENSE_ABS_THR is programmable in 1 dB steps from -7 dB to + 7dB. Table 64 and Table 65 show the RSSI readout values at the CS threshold at 2.4 kbps and 250 kbps data rate respectively. The default CARRIER_SENSE_ABS_THR = 0 (0 dB) and MAGN_TARGET = 3 (33 dB) have been used.
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MAX_DVGA_GAIN[1:0] 00 000 MAX_LNA_GAIN[2:0] 001 010 011 100 101 110 111 -99 -97 -93.5 -91.5 -90.5 -88 -84.5 -82.5 01 -93 -90.5 -87 -86 -84 -82.5 -78.5 -76 10 -87 -85 -82 -80 -78 -76 -73 -70 11 -81.5 -78.5 -76 -74 -72.5 -70 -67 -64
Table 64: Typical RSSI value in dBm at CS threshold with default MAGN_TARGET at 2.4 kbps MAX_DVGA_GAIN[1:0] 00 000 MAX_LNA_GAIN[2:0] 001 010 011 100 101 110 111 -96 -94.5 -92.5 -91 -87.5 -85 -83 -78 01 -90 -89 -87 -85 -82 -79.5 -76.5 -72 10 -84 -83 -81 -78.5 -76 -73.5 -70.5 -66 11 -78.5 -77.5 -75 -73 -70 -67.5 -65 -60
Table 65: Typical RSSI value in dBm at CS threshold with default MAGN_TARGET at 250 kbps If the threshold is to be set high, e.g. only strong signals are wanted, the threshold should be adjusted upwards by first reducing the MAX_LNA_GAIN value and then the MAX_DVGA_GAIN value. This will reduce power consumption in the receiver front end, since the highest gain settings are avoided. The MAGN_TARGET setting is a compromise between blocker tolerance/selectivity and sensitivity. The value sets the desired signal level in the channel into the demodulator. Increasing this value reduces the headroom for blockers, and therefore close-in selectivity. 15.10.6 CS relative threshold The relative threshold detects sudden changes in the measured signal level. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor. The register field AGCCTRL1.CARRIER_SENSE_REL_THR is used to enable/disable relative CS, and to select threshold of 6 dB, 10 dB or 14 dB RSSI change. 15.10.7 Clear Channel Assessment (CCA) The Clear Channel Assessment is used to indicate if the current channel is free or busy. The current CCA state is viewable in the PKTSTATUS register MCSM1.CCA_MODE selects the mode to use when determining CCA. When the STX or SFSTXON command strobe is given while CC2510FX/CC2511Fx is in the RX state, the TX state is only entered if the clear
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channel requirements are fulfilled. The chip will otherwise remain in RX. This feature is called TX if CCA. Four CCA requirements can be programmed: * * * * Always (CCA disabled, always goes to TX) If RSSI is below threshold Unless currently receiving a packet Both the above (RSSI below threshold and not currently receiving a packet) relatively long periods of faulty reception (burst errors). The
CC2510FX/CC2511Fx is convolutional coding, in
FEC
scheme
adopted
for
which n bits are generated based on k input bits and the m most recent input bits, forming a code stream able to withstand a certain number of bit errors between each coding state (the m-bit window). The convolutional coder is a rate 1/2 code with a constraint length of m=4. The coder codes one input bit and produces two output bits; hence, the effective data rate is halved. 15.11.1 Interleaving Data received through real radio channels will often experience burst errors due to interference and time-varying signal strengths. In order to increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will become single errors spread apart.
15.10.8 Link Quality Indicator (LQI) The Link Quality Indicator is a metric of the current quality of the received signal. If PKTCTRL1.APPEND_STATUS is enabled, the value is automatically appended to the end of each received packet. The value can also be read from the LQI status register. The LQI is calculated over the 64 symbols following the sync word (first 8 packet bytes). LQI is best used as a relative measurement of the link quality, since the value is dependent on the modulation format. 15.11 Forward Error Correction with Interleaving
CC2510FX/CC2511Fx employs matrix interleaving,
which is illustrated in Figure 49. The on-chip interleaving and de-interleaving buffers are 4 x 4 matrices. In the transmitter, the data bits are written into the rows of the matrix, whereas the bit sequence to be transmitted is read from the columns of the matrix and fed to the rate 1/2 convolutional coder. Conversely, in the receiver, the received symbols are written into the columns of the matrix, whereas the data passed onto the convolutional decoder is read from the rows of the matrix. When FEC and interleaving is used at least one extra byte is required for trellis termination. In addition, the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer (two bytes). The packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet, so that the total length of the data to be interleaved is an even number. Note that these extra bytes are invisible to the user, as they are removed before the received packet enters the RFD data register. When FEC and interleaving is used the minimum data payload is 2 bytes in fixed and variable packet length mode.
CC2510FX/CC2511Fx has built-in support for
Forward Error Correction (FEC). To enable this option, set MDMCFG1.FEC_EN to 1. FEC is employed on the data field and CRC word in order to reduce the gross bit error rate when operating near the sensitivity limit. Redundancy is added to the transmitted data in such a way that the receiver can restore the original data in the presence of some bit errors. The use of FEC allows correct reception at a lower SNR, thus extending communication range. Alternatively, for a given SNR, using FEC decreases the bit error rate (BER). As the packet error rate (PER) is related to BER by:
PER = 1 - (1 - BER ) packet _ length ,
a lower BER can be used to allow significantly longer packets, or a higher percentage of packets of a given length, to be transmitted successfully. Finally, in realistic ISM radio environments, transient and time-varying phenomena will produce occasional errors even in otherwise good reception conditions. FEC will mask such errors and, combined with interleaving of the coded data, even correct
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1) Storing coded data
2) Transmitting interleaved data Demodulator
3) Receiving interleaved data
4) Passing on data to decoder
Modulator
TX Data
Decoder Receiver
Encoder
RX Data
Transmitter
Figure 49: General principle of matrix interleaving
15.12 Radio Control
CC2510FX/CC2511Fx has a built-in state machine
that is used to switch between different operation states (modes). The change of state is done by using command strobes. A simplified state diagram, together with typical usage and current consumption, is
shown in Figure 43 on page 192. The complete radio control state diagram is shown in Figure 50. The numbers refer to the state number readable in the MARCSTATE status register. This register is primarily for test purposes.
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Figure 50: Complete Radio Control State Diagram 15.12.1 Active Modes The CC2510FX/CC2511Fx radio has two active modes: receive and transmit. These modes are activated directly by the CPU by writing the SRX and STX command strobes to the RFST register. The frequency synthesizer must be calibrated regularly. CC2510FX/CC2511Fx has one manual calibration option (using the SCAL strobe), and three automatic calibration options. The automatic calibration options are controlled by the MCSM0.FS_AUTOCAL setting: * * Calibrate when going from IDLE to either RX or TX (or FSTXON) Calibrate when going from either RX or TX to IDLE
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* Calibrate every fourth time when going from either RX or TX to IDLE setting. RX/TX and TX/RX turnaround times are constant. The calibration time is constant 18739 clock periods. Table 66 shows timing in crystal clock cycles for key state transitions. Power on time and XOSC start-up times are variable, but within the limits stated in Table 9. Note that in a frequency hopping spread spectrum or a multi-channel protocol the calibration time can be reduced from 721 s to approximately 150 s. This is explained in section 15.18.2.
The calibration takes a constant number of XOSC cycles (see Table 66 for timing details). When RX is activated, the chip will remain in receive mode until the RX termination timer expires (see section 15.12.3) or a packet has been successfully received. Note: the probability that a false sync word is detected can be reduced by using PQT, CS, maximum sync word length and sync word qualifier mode as describe in section 15.10. After a packet is successfully received the radio controller will then go to the state indicated by the MCSM1.RXOFF_MODE setting. The possible states are: * * IDLE FSTXON: Frequency synthesizer on and ready at the TX frequency. Activate TX with STX. TX: Start sending preambles RX: Start search for a new packet
Description Idle to RX, no calibration Idle to RX, with calibration Idle to TX/FSTXON, no calibration Idle to TX/FSTXON, with calibration TX to RX switch RX to TX switch RX or TX to IDLE, no calibration RX or TX to IDLE, with calibration Manual calibration
XOSC periods 2298 ~21037 2298 ~21037 560 250 2 ~18739 ~18739
26MHz crystal 88.4s 809s 88.4s 809s 21.5s 9.6s 0.1s 721s 721s
* *
Similarly, when TX is active the chip will remain in the TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinations are the same as for RX. The CPU can change the state from RX to TX and vice versa by using the command strobes. If the radio controller is currently in transmit and the SRX strobe is written, the current transmission will be ended and the transition to RX will be done. If the radio controller is in RX when the STX or SFSTXON command strobes are issued, the "TX if clear channel" function will be used. If the channel is not clear, the chip will remain in RX. The MCSM1.CCA_MODE setting controls the conditions for clear channel assessment. See section 15.10.7 on page 206 for details. The SIDLE command strobe can always be issued to force the radio controller to go to the IDLE state. 15.12.2 Timing
Table 66: State transition timing 15.12.3 RX Termination Timer
CC2510FX/CC2511Fx has optional functions for
automatic termination of RX after a programmable time. The termination timer starts when enabling the demodulator. The timeout is programmable with the MCSM2.RX_TIME setting. When the timer expires, the radio controller will check the condition for staying in RX; if the condition is not met, RX will terminate. After the timeout, the condition will be checked continuously. The programmable conditions are: * * MCSM2.RX_TIME_QUAL=0: Continue receive if sync word has been found MCSM2.RX_TIME_QUAL=1: Continue receive if sync word has been found or preamble quality is above threshold (PQT)
CC2510FX/CC2511Fx,
The radio controller controls most timing in such as synthesizer calibration, PLL lock and RT/TX turnaround times. Timing from IDLE to RX and IDLE to TX is constant, dependent on the auto calibration
If the system can expect the transmission to have started when enabling the receiver, the MCSM2.RX_TIME_RSSI function can be used. The radio controller will then terminate RX if the first valid carrier sense sample indicates no carrier (RSSI below threshold). See Section
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15.10.4 on page 205 for details on Carrier Sense. For OOK modulation, lack of carrier sense is only considered valid after eight symbol periods. Thus, the MCSM2.RX_TIME_RSSI function can be used in OOK mode when the distance between "1" symbols is 8 or less. If RX terminates due to no carrier sense when the MCSM2.RX_TIME_RSSI function is used, or if no sync word was found when using the MCSM2.RX_TIME timeout function, the chip will always go back to IDLE. Otherwise, the MCSM1.RXOFF_MODE setting determines the state to go to when RX ends. 15.13 Frequency Programming is designed to minimize the programming needed in a channel-oriented system. To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissa and exponent respectively. The base or start frequency is set by the 24 bit frequency word located in the FREQ2, FREQ1 and FREQ0 registers. This word will typically be set to the centre of the lowest channel frequency that is to be used. The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN, which is multiplied by the channel offset. The resultant carrier frequency is given by:
CC2510FX/CC2511Fx
The
frequency
programming
in
f carrier =
f XOSC FREQ + CHAN ( 256 + CHANSPC _ M ) 2 CHANSPC _ E - 2 2 16
(
(
))
With a 26 MHz crystal the maximum channel spacing is 405 kHz. To get e.g. 1 MHz channel spacing one solution is to use 333 kHz channel spacing and select each third channel in CHANNR.CHAN. The preferred IF frequency is programmed with the FSCTRL1.FREQ_IF register. The IF frequency is given by:
15.14.1 VCO and PLL Self-Calibration The VCO characteristics will vary with temperature and supply voltage changes, as well as the desired operating frequency. In order to ensure reliable operation, CC2510FX/CC2511Fx includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLL calibration is given in Table 66 on page 210. The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated when the SCAL command strobe is activated in the IDLE mode. Note that the calibration values are maintained in power-down modes PM2/3, so the calibration is still valid after waking up from these power-down modes (unless supply voltage or temperature has changed significantly).
f IF =
f XOSC FREQ _ IF 210
Note that the SmartRF(R) Studio software automatically calculates the optimum FSCTRL1.FREQ_IF register setting based on channel spacing and channel filter bandwidth. If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. Hence, the frequency programming should only be updated when the radio is in the IDLE state. 15.14 VCO The VCO is completely integrated on-chip.
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15.15 Output Power Programming The RF output power level from the device has two levels of programmability, as illustrated in Figure 51. Firstly, the PA_TABLE7PA_TABLE0 registers can hold up to eight user selected output power settings. Secondly, the 3-bit FREND0.PA_POWER value selects which PA_TABLE7-0 register to use. This two-level functionality provides flexible PA power ramp up and ramp down at the start and end of transmission. In each case, all the PA power settings from PA_TABLE from index 0 up to the FREND0.PA_POWER value are used. The power ramping at the start and at the end of a packet can be turned off by setting FREND0.PA_POWER to zero and then programming the desired output power in PA_TABLE0. Table 67 contains recommended PA_TABLE settings for various output levels and frequency bands, together with current consumption in the RF transceiver.
PA_TABLE7[7:0] PA_TABLE6[7:0] PA_TABLE5[7:0] PA_TABLE4[7:0] PA_TABLE3[7:0] PA_TABLE2[7:0] PA_TABLE1[7:0] PA_TABLE0[7:0]
Index into PA_TABLE7-0
The PA uses this setting. Settings 0 to PA_POWER are used during ramp-up at start of transmission and ramp-down at end of transmission, and for OOK modulation.
e.g 6 PA_POWER[2:0] in FREND0 register
The SmartRF(R) Studio software should be used to get optimum PATABLE settings for various output powers.
Figure 51: PA_POWER and PA_TABLE7-0
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Output power [dBm] Typical +25 C, 3.0 V (-55 or less) -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 1 0x00 0x44 0x41 0x4C 0x53 0x83 0x46 0x4A 0x86 0x66 0xC6 0x69 0x99 0x7F 0xAA 0xBF 0xFB 0xFF 8.9 10.1 10.0 11.7 11.1 10.9 10.5 11.7 11.0 12.9 11.5 14.1 13.6 15.4 16.7 18.5 21.6 21.9 Setting Current consumption, typ. [mA]
Table 67: Optimum PA_TABLE settings for various output power levels (subject to changes) 15.16 Selectivity Graphs Figure 52 to Figure 56 show the typical selectivity performance (adjacent and alternate rejection).
50
40
30 Selectivity [dB]
20
10
0 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
-10 Frequency offset [MHz]
Figure 52: Typical selectivity at 2.4 kbps. IF frequency is 273.9 kHz. MDMCFG2.DEM_DCFILT_OFF = 1
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40 35 30 25 Selectivity [dB] 20 15 10 5 0 -1 -0.8 -0.6 -0.4 -0.2 -5 -10 Fre que ncy offse t [M Hz] 0 0.2 0.4 0.6 0.8 1
Figure 53: Typical selectivity at 10 kbps. IF frequency is 273.9 kHz. MDMCFG2.DEM_DCFILT_OFF = 1
50
40
30
Selectivity [dB]
20
10
0 -3 -2 -1 -10 0 1 2 3
-20 Frequency offset [MHz]
Figure 54: Typical selectivity at 250 kbps. IF frequency is 177.7 kHz. MDMCFG2.DEM_DCFILT_OFF = 0
50
40
30
Selectivity [dB]
20
10
0 -3 -2 -1 -10 0 1 2 3
-20 Frequency offset [MHz]
Figure 55: Typical selectivity at 250 kbps. IF frequency is 457 kHz. MDMCFG2.DEM_DCFILT_OFF = 1
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35 30 25 20 15 Selectivity [dB] 10 5 0 -3 -2 -1 -5 -10 -15 -20 Frequency offset [MHz] 0 1 2 3
Figure 56: Typical selectivity at 500 kbps. IF frequency is 307.4 kHz. MDMCFG2.DEM_DCFILT_OFF = 0
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15.17 Antenna Interface The performance. It is the customer's responsibility to ensure that the system complies with regulations. 15.18.2 Frequency Hopping and Multi-Channel Systems The 2.400 - 2.4835 GHz band is shared by many systems both in industrial, office and home environments. It is therefore recommended to use frequency hopping spread spectrum (FHSS) or a multi-channel protocol because the frequency diversity makes the system more robust with respect to interference from other systems operating in the same frequency band. FHSS also combats multipath fading.
CC2510FX/CC2511Fx share two common pins and
are designed for a simple, low-cost matching and balun network on the printed circuit board. The receive- and transmit switching at the CC2510FX/CC2511Fx front-end is controlled by a dedicated on-chip function, eliminating the need for an external RX/TX-switch. A few passive external components combined with the internal RX/TX switch/termination circuitry ensures match in both RX and TX mode. Although CC2510FX/CC2511Fx has a balanced RF input/output, the chip can be connected to a single-ended antenna with few external low cost capacitors and inductors. The passive matching/filtering network connected to CC2510FX/CC2511Fx should have the following differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna: Zout = 80 + j74 To ensure optimal matching of the
balanced
RF
input
and
output
of
CC2510FX/CC2511Fx is highly suited for FHSS or
multi-channel systems due to its agile frequency synthesizer and effective communication interface. Using the packet handling support and data buffering is also beneficial in such systems as these features will significantly offload the host controller. Charge pump current, VCO current and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for CC2510FX/CC2511Fx. There are 3 ways of obtaining the calibration data from the chip: 1) Frequency hopping with calibration for each hop. The PLL calibration time is approximately 720 s. 2) Fast frequency hopping without calibration for each hop can be done by calibrating each frequency at startup and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values in MCU memory. Between each frequency hop, the calibration process can then be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. The PLL turn on time is approximately 90 s. 3) Run calibration on a single frequency at startup. Next write 0hex to FSCAL3[5:4] to disable the charge pump calibration. After writing to FSCAL3[5:4] strobe SRX (or STX) with MCSM0.FS_AUTOCAL = 1 for each new frequency hop. That is, VCO current and VCO capacitance calibration is done but not charge pump current calibration. When charge pump current calibration is disabled the calibration time is reduced from approximately 720 s to approximately 150 s.
CC2510FX/CC2511Fx differential output it is
recommended to follow the CC2510EM reference designs as closely as possible. Gerber files for the reference designs are available for download from the Chipcon website. 15.18 System Guidelines considerations and
15.18.1 SRD Regulations International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation are allowed to operate in the 2.45 GHz bands worldwide. The most important regulations are EN 300 440 and EN 300 328 (Europe), FCC CFR47 part 15.247 and 15.249 (USA), and ARIB STD-T66 (Japan). A summary of the most important aspects of these regulations can be found in Application Note AN032 SRD regulations for license-free transceiver operation in the 2.4 GHz band, available from the Chipcon website. Please note that compliance with regulations is dependent on complete system
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There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. Solution 3) gives approximately 570 s smaller blanking interval than solution 1). 15.18.3 Wideband Modulation Spread Spectrum not Using The frequency offset between an `external' transmitter and the receiver is measured in the CC2510FX/CC2511Fx and can be read back from the FREQEST status register. The measured frequency offset can be used to calibrate the frequency using the `external' transmitter as the reference. That is, the received signal of the device will match the receiver's channel filter better. In the same way the centre frequency of the transmitted signal will match the `external' transmitter's signal. 15.18.7 Spectrum Efficient Modulation
Digital modulation systems under FCC part 15.247 includes FSK and GFSK modulation. A maximum peak output power of +30 dBm is allowed if the 6 dB bandwidth of the modulated signal is not less than 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dBm in any 3 kHz band. Operating at high data rates and high frequency separation, the CC2500 is suited for systems targeting compliance with digital modulation system as defined by FCC part 15.247. An external power amplifier is needed to increase the output above +0 dBm. 15.18.4 Data Burst Transmissions
CC2510FX/CC2511Fx also has the possibility to
use Gaussian shaped FSK (GFSK). This spectrum-shaping feature improves adjacent channel power (ACP) and occupied bandwidth. In `true' FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift `softer', the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth using GFSK. 15.18.8 Low Cost Systems As the CC2510FX/CC2511Fx provides 500 kbps multi-channel performance without any external filters, a very low cost system can be made. A differential antenna will eliminate the need for a balun, and the DC biasing can be achieved in the antenna topology, see Figure 7. A HC-49 type SMD crystal is used in the CC2510FX EM reference design. Note that the crystal package strongly influences the price. In a size constrained PCB design a smaller, but more expensive, crystal may be used. 15.18.9 Battery Operated Systems In low power applications, the low power modes PM2 or PM3 with should be used when the CC2510FX/CC2511Fx is not active. The Sleep Timer Wake-on-Radio functionality should be used in low power applications. 15.18.10 Increasing Output Power
CC2510FX/CC2511Fx
The
maximum data rate of opens up for burst transmissions. A low average data rate link (say 10 kbps), can be realized using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (say 500 kbps) will reduce the time in active mode, and hence also reduce the average current consumption significantly. Reducing the time in active mode will reduce the likelihood of collisions with other systems, e.g. WLAN. 15.18.5 Continuous Transmissions
high
CC2510FX/CC2511Fx opens up for continuous
In
data
streaming
applications
the
transmissions at 500 kbps effective data rate. As the modulation is done with an I/Q upconverter with LO I/Q-signals coming from a closed loop PLL, there is no limitation in the length of a transmission. (Open loop modulation used in some transceivers often prevents this kind of continuous data streaming and reduces the effective data rate.) 15.18.6 Crystal Drift Compensation The CC2510FX/CC2511Fx has a very fine frequency resolution. This feature can be used to compensate for frequency offset and drift.
In some applications it may be necessary to extend the link range. Adding an external power amplifier is the most effective way of doing this. The power amplifier should be inserted between the antenna and the balun, and two
Page 217 of 252
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CC2510FX / CC2511Fx
T/R switches are needed to disconnect the PA in RX mode. See Error! Reference source not found..
Antenna
Filter
PA Balun
CC2510F X/CC251
T/R switch
T/R switch
Figure 57. Block diagram of CC2510FX/CC2511Fx usage with external power amplifier
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15.19 Radio Registers This section describes all RF registers used for control and status for the radio. The RF registers reside in XDATA memory space in the region 0xDF00-0xDF3D. Table 68 gives an overview of register addresses while the remaining tables in this section describe each register.
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XDATA Address 0xDF00 0xDF01 0xDF02 0xDF03 0xDF04 0xDF05 0xDF06 0xDF07 0xDF08 0xDF09 0xDF0A 0xDF0B 0xDF0C 0xDF0D 0xDF0E 0xDF0F 0xDF10 0xDF11 0xDF12 0xDF13 0xDF14 0xDF15 0xDF16 0xDF17 0xDF18 0xDF19 0xDF1A 0xDF1B 0xDF1C 0xDF1D 0xDF1E 0xDF1F 0xDF20 0xDF21 0xDF22 0xDF23 0xDF24 0xDF25 0xDF27 0xDF28 0xDF29 0xDF2A 0xDF2B 0xDF2C 0xDF2D 0xDF2E 0xDF2F 0xDF30 0xDF31 Register SYNC1 SYNC0 PKTLEN PKTCTRL1 PKTCTRL0 ADDR CHANNR FSCTRL1 FSCTRL0 FREQ2 FREQ1 FREQ0 MDMCFG4 MDMCFG3 MDMCFG2 MDMCFG1 MDMCFG0 DEVIATN MCSM2 MCSM1 MCSM0 FOCCFG BSCFG AGCTRL2 AGCTRL1 AGCTRL0 FREND1 FREND0 FSCAL3 FSCAL2 FSCAL1 FSCAL0 PA_TABLE7 PA_TABLE6 PA_TABLE5 PA_TABLE4 PA_TABLE3 PA_TABLE2 PA_TABLE1 PA_TABLE0 IOCFG2 IOCFG1 IOCFG0 Description Sync word, high byte Sync word, low byte Packet length Packet automation control Packet automation control Device address Channel number Frequency synthesizer control Frequency synthesizer control Frequency control word, high byte Frequency control word, middle byte Frequency control word, low byte Modem configuration Modem configuration Modem configuration Modem configuration Modem configuration Modem deviation setting Main Radio Control State Machine configuration Main Radio Control State Machine configuration Main Radio Control State Machine configuration Frequency Offset Compensation configuration Bit Synchronization configuration AGC control AGC control AGC control Front end RX configuration Front end TX configuration Frequency synthesizer calibration Frequency synthesizer calibration Frequency synthesizer calibration Frequency synthesizer calibration Reserved Reserved Reserved Reserved Reserved Reserved PA output power setting PA output power setting PA output power setting PA output power setting PA output power setting PA output power setting PA output power setting PA output power setting
GDO2 output pin configuration GDO1 output pin configuration GDO0 output pin configuration
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XDATA Address 0xDF36 0xDF37 0xDF38 0xDF39 0xDF3A 0xDF3B 0xDF3C 0xDF3D Register PARTNUM VERSION FREQEST LQI RSSI MARCSTATE PKSTATUS VCO_VC_DAC Description Chip Identifier configuration Frequency Offset Estimate Link Quality Indicator Received Signal Strength Indication Main Radio Control State Packet status PLL calibration current
Table 68: Overview of RF registers
0xDF2F: IOCFG2 - GDO2 output pin configuration
Bit 7 6 5:0 Field Name Reset R/W R0 0 0x00 R/W R/W Description Reserved Invert output, i.e. select active low / high Debug output on P1_7 pin. See Table 69 for description of internal signals which can be output on this pin for debug purpose
GDO2_INV GDO2_CFG[5:0]
0xDF30: IOCFG1 - GDO1 output pin configuration
Bit 7 6 5:0 Field Name GDO_DS Reset 0 0 0x00 R/W R/W R/W R/W Description Set high (1) or low (0) output drive strength on the GDO pins. Invert output, i.e. select active low / high Debug output on P1_6 pin. See Table 69 for description of internal signals which can be output on this pin for debug purpose
GDO1_INV GDO1_CFG[5:0]
0xDF31: IOCFG0 - GDO0 output pin configuration
Bit 7 6 5:0 Field Name TEMP_SENSOR_ENABLE Reset 0 0 0x00 R/W R/W R/W R/W Description Enable analog temperature sensor. Write 0 in all other register bits when using temperature sensor. Invert output, i.e. select active low / high Debug output on P1_5 pin. See Table 69 for description of internal signals which can be output on this pin for debug purpose
GDO0_INV GDO0_CFG[5:0]
0xDF00: SYNC1 - Sync word, high byte
Bit 7:0 Field Name SYNC[15:8] Reset 0xD3 R/W R/W Description 8 MSB of 16-bit sync word
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0xDF01: SYNC0 - Sync word, low byte
Bit 7:0 Field Name SYNC[7:0] Reset 0x91 R/W R/W Description 8 LSB of 16-bit sync word
0xDF02: PKTLEN - Packet length
Bit 7:0 Field Name PACKET_LENGTH Reset 0xFF R/W R/W Description Indicates the packet length when fixed length packets are enabled. If variable length packets are used, this value indicates the maximum length packets allowed.
0xDF03: PKTCTRL1 - Packet automation control
Bit 7:5 Field Name PQT[2:0] Reset 000 R/W R/W Description Preamble quality estimator threshold. The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit, and decreases the counter by 4 each time a bit is received that is the same as the last bit. The counter saturates at 0 and 31. A threshold of 4*PQT for this counter is used to gate sync word detection. When PQT=0 a sync word is always accepted. 4:3 2 APPEND_STATUS 00 1 R0 R/W Reserved When enabled, two status bytes will be appended to the payload of the packet. The status bytes contain RSSI and LQI values, as well as the CRC OK flag. Controls address check configuration of received packages. Setting 0 (00) 1 (01) 2 (10) 3 (11) Address check configuration No address check Address check, no broadcast Address check, 0 (0x00) broadcast Address check, 0 (0x00) and 255 (0xFF) broadcast
1:0
ADR_CHK[1:0]
00
R/W
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0xDF04: PKTCTRL0 - Packet automation control
Bit 7 6 Field Name WHITE_DATA Reset 0 1 R/W R0 R/W Description Reserved Turn data whitening on / off 0: Whitening off 1: Whitening on Data whitening can only be used when PKTCTRL0.CC2400_EN = 0 (default). 5:4 PKT_FORMAT[1:0] 00 R/W Format of RX and TX data Setting 0 (00) 1 (01) Packet format Normal mode, use FIFOs for RX and TX Serial Synchronous mode, used for backwards compatibility Random TX mode; sends random data using PN9 generator. Used for test. Works as normal mode, setting 0 (00), in RX. Asynchronous transparent mode. Data in on GDO0 and Data out on either of the GDO pins
2 (10)
3 (11) 3 CC2400_EN 0 R/W
Enable CC2400 support. Use same CRC implementation as CC2400.
PKTCTRL0.WHITE_DATA must be 0 if PKTCTRL0.CC2400_EN = 1.
2 CRC_EN 1 R/W 1: CRC calculation in TX and CRC check in RX enabled 0: CRC disabled for TX and RX 1:0 LENGTH_CONFIG[1:0] 01 R/W Configure the packet length Setting 0 (00) 1 (01) 2 (10) 3 (11) Packet length configuration Fixed length packets, length configured in PKTLEN register Variable length packets, packet length configured by the first byte after sync word Enable infinite length packets Reserved
0xDF05: ADDR - Device address
Bit 7:0 Field Name DEVICE_ADDR[7:0] Reset 0x00 R/W R/W Description Address used for packet filtration. Optional broadcast addresses are 0 (0x00) and 255 (0xFF).
0xDF06: CHANNR - Channel number
Bit 7:0 Field Name CHAN[7:0] Reset 0x00 R/W R/W Description The 8-bit unsigned channel number, which is multiplied by the channel spacing setting and added to the base frequency.
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0xDF07: FSCTRL1 - Frequency synthesizer control
Bit 7:5 4:0 Field Name FREQ_IF[4:0] Reset 000 01111 R/W R0 R/W Description Not used The desired IF frequency to employ in RX. Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator.
f IF =
f XOSC FREQ _ IF 210
The default value gives an IF frequency of 381kHz, assuming a 26.0MHz crystal.
0xDF08: FSCTRL0 - Frequency synthesizer control
Bit 7:0 Field Name FREQOFF[7:0] Reset 0x00 R/W R/W Description Frequency offset added to the base frequency before being used by the FS. (2-complement). Resolution is FXTAL/2 (1.5kHz-1.7kHz); range is 186kHz to 217kHz, dependent of XTAL frequency. The SAFC strobe command and the automatic AFC mechanism add the current FREQEST value to FREQOFF.
14
0xDF09: FREQ2 - Frequency control word, high byte
Bit 7:6 5:0 Field Name FREQ[23:22] FREQ[21:16] Reset 00 0x1E R/W R R/W Description FREQ[23:22] is always binary 01 (the FREQ2 register is in the range 85 to 95 with 26MHz-28MHz crystal) FREQ[23:0] is the base frequency for the frequency synthesizer in 16 increments of FXOSC/2 .
f carrier =
f XOSC FREQ [23 : 0] 216
The default frequency word gives a base frequency of 2464MHz, assuming a 26.0MHz crystal. With the default channel spacing settings, the following FREQ2 values and channel numbers can be used: FREQ2 91 (0x5B) 92 (0x5C) 93 (0x5D) 94 (0x5E) Base frequency 2386MHz 2412MHz 2438MHz 2464MHz Frequency range (CHAN numbers) 2400.2MHz-2437MHz (71-255) 2412MHz-2463MHz (0-255) 2431MHz-2483.4MHz (0-227) 2464MHz-2483.4MHz (0-97)
0xDF0A: FREQ1 - Frequency control word, middle byte
Bit 7:0 Field Name FREQ[15:8] Reset 0xC4 R/W R/W Description Ref. FREQ2 register
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0xDF0B: FREQ0 - Frequency control word, low byte
Bit 7:0 Field Name FREQ[7:0] Reset 0xEC R/W R/W Description Ref. FREQ2 register
0xDF0C: MDMCFG4 - Modem configuration
Bit 7:6 5:4 Field Name CHANBW_E[1:0] CHANBW_M[1:0] Reset 10 00 R/W R/W R/W Sets the decimation ratio for the delta-sigma ADC input stream and thus the channel bandwidth. Description
BWchannel =
f XOSC 8 (4 + CHANBW _ M )*2CHANBW _ E
The default values give 203kHz channel filter bandwidth, assuming a 26.0MHz crystal. 3:0 DRATE_E[3:0] 1100 R/W The exponent of the user specified symbol rate
0xDF0D: MDMCFG3 - Modem configuration
Bit 7:0 Field Name DRATE_M[7:0] Reset 0x22 R/W R/W Description The mantissa of the user specified symbol rate. The symbol rate is configured using an unsigned, floating-point number th with 9-bit mantissa and 4-bit exponent. The 9 bit is a hidden `1'. The resulting data rate is:
RDATA =
(256 + DRATE _ M ) 2 DRATE _ E f
2 28
XOSC
The default values give a data rate of 115.051kbps (closest setting to 115.2kbps), assuming a 26.0MHz crystal.
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0xDF0E: MDMCFG2 - Modem configuration
Bit 7 Field Name DEM_DCFILT_OFF Reset 0 R/W R/W Description Disable digital DC blocking filter before demodulator. 0 = Enable (better sensitivity for data rates 250 kbps) 1 = Disable (reduced power consumption) The recommended IF frequency changes when the DC blocking is disabled. 6:4 MOD_FORMAT[2:0] 000 R/W The modulation format of the radio signal Setting 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) 3 MANCHESTER_EN 0 R/W Modulation format 2-FSK GFSK OOK MSK
Enables Manchester encoding/decoding. 0 = Disable 1 = Enable
2:0
SYNC_MODE[2:0]
010
R/W
Combined sync-word qualifier mode. The values 0 (000) and 4 (100) disables sync word transmission in TX and sync word detection in RX. The values 1 (001), 2 (001), 5 (101) and 6 (110) enables 16-bit sync word transmission in TX and 16bits sync word detection in RX. Only 15 of 16 bits need to match in RX when using setting 1 (001) or 5 (101). The values 3 (011) and 7 (111) enables repeated sync word transmission in RX and 32-bits sync word detection in RX (only 30 of 32 bits need to match). Setting 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Sync-word qualifier mode No preamble/sync 15/16 sync word bits detected 16/16 sync word bits detected 30/32 sync word bits detected No preamble/sync, carrier-sense above threshold 15/16 + carrier-sense above threshold 16/16 + carrier-sense above threshold 30/32 + carrier-sense above threshold
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0xDF0F: MDMCFG1 - Modem configuration
Bit 7 Field Name FEC_EN Reset 0 R/W R/W Description Enable Forward Error Correction (FEC) with interleaving for packet payload 0 = Disable 1 = Enable 6:4 NUM_PREAMBLE[2:0] 010 R/W Sets the minimum number of preamble bytes to be transmitted Setting 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) 3:2 1:0 CHANSPC_E[1:0] 0 10 R0 R/W Reserved 2 bit exponent of channel spacing Number of preamble bytes 2 3 4 6 8 12 16 24
0xDF10: MDMCFG0 - Modem configuration
Bit 7:0 Field Name CHANSPC_M[7:0] Reset 0xF8 R/W R/W Description 8-bit mantissa of channel spacing (initial 1 assumed). The channel spacing is multiplied by the channel number CHAN and added to the base frequency. It is unsigned and has the format:
f CHANNEL =
f XOSC (256 + CHANSPC _ M ) 2 CHANSPC _ E CHAN 218
The default values give 199.951kHz channel spacing (the closest setting to 200kHz), assuming 26.0MHz crystal frequency.
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0xDF11: DEVIATN - Modem deviation setting
Bit 7 6:4 3 2:0 Field Name DEVIATION_E[2:0] DEVIATION_M[2:0] Reset 0 100 0 111 R/W R0 R/W R0 R/W Description Reserved Deviation exponent Reserved When MSK modulation is enabled: Sets fraction of symbol period used for phase change. When FSK modulation is enabled: Deviation mantissa, interpreted as a 4-bit value with MSB implicit 1. The resulting FSK deviation is given by:
f dev =
f xosc (8 + DEVIATION _ M ) 2 DEVIATION _ E 17 2
The default values give 47.607kHz deviation, assuming 26.0MHz crystal frequency.
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0xDF12: MCSM2 - Main Radio Control State Machine configuration
Bit 7:5 4 Field Name Reserved RX_TIME_RSSI 0 Reset R/W R0 R/W Description Reserved Direct RX termination based on RSSI measurement (carrier sense). For OOK modulation, RX times out if there is no carrier sense in the first 8 symbol periods. When the RX_TIME timer expires the chip stays in RX mode if sync word is found when RX_TIME_QUAL=0, or either sync word is found or PQT is set when RX_TIME_QUAL=1. Timeout for sync word search in RX. The timeout is relative to the programmed EVENT0 timeout, which means that the duty cycle can be set in wake-on-radio (WOR) mode.
3
RX_TIME_QUAL
0
R/W
2:0
RX_TIME[2:0]
7 (111)
R/W
The RX timeout in s is given by EVENT0*C(RX_TIME, WOR_RES), where C is given by the table below (XOSC = 26 MHz): RX_TIME[2:0] 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) WOR_RES = 0 3.6058 1.8029 0.9014 0.4507 0.2254 0.1127 0.0563 Until end of packet WOR_RES = 1 18.0288 9.0144 4.5072 2.2536 1.1268 0.5634 0.2817 WOR_RES = 2 32.4519 16.2260 8.1130 4.0565 2.0282 1.0141 0.5071 WOR_RES = 3 46.8750 23.4375 11.7188 5.8594 2.9297 1.4648 0.7324
As an example, EVENT0 = 34666, WOR_RES = 0 and RX_TIME = 6 corresponds to 1.96 ms RX timeout, 1 s polling interval and 0.195% duty cycle. Note that WOR_RES should be 0 or 1 when using WOR. The duty cycle is approximated by: RX_TIME[2:0] 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) WOR_RES = 0 12.50% 6.250% 3.125% 1.563% 0.781% 0.391% 0.195% Until end of packet WOR_RES = 1 1.95% 9765ppm 4883ppm 2441ppm NA NA NA
Note that the RC oscillator must be enabled in order to use setting 0-6, because the timeout counts RC oscillator periods. WOR mode does not need to be enabled. The timeout counter resolution is limited: With RX_TIME=0, the timeout count is given by the 13 MSBs of EVENT0, decreasing to the 7 MSBs of EVENT0 with RX_TIME=6.
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0xDF13: MCSM1 - Main Radio Control State Machine configuration
Bit 7:6 5:4 Field Name CCA_MODE[1:0] Reset 00 11 R/W R0 R/W Description Reserved Selects CCA_MODE; Reflected in CCA signal Setting 0 (00) 1 (01) 2 (10) 3 (11) 3:2 RXOFF_MODE[1:0] 00 R/W Clear channel indication Always If RSSI below threshold Unless currently receiving a packet If RSSI below threshold unless currently receiving a packet
Select what should happen when a packet has been received Setting 0 (00) 1 (01) 2 (10) 3 (11) Next state after finishing packet reception IDLE FSTXON TX Stay in RX
1:0
TXOFF_MODE[1:0]
00
R/W
Select what should happen when a packet has been sent (TX) Setting 0 (00) 1 (01) 2 (10) 3 (11) Next state after finishing packet transmission IDLE FSTXON Stay in TX (start sending preamble) RX
0xDF14: MCSM0 - Main Radio Control State Machine configuration
Bit 7:6 5:4 Field Name FS_AUTOCAL[1:0] Reset 00 00 R/W R0 R/W Description Reserved Automatically calibrate when going to RX or TX, or back to IDLE Setting 0 (00) 1 (01) 2 (10) 3 (11) When to perform automatic calibration Never (manually calibrate using SCAL strobe) When going from IDLE to RX or TX (or FSTXON) When going from RX or TX back to IDLE Every 4 time when going from RX or TX to IDLE
th
In some automatic wake-on-radio (WOR) applications, using setting 3 (11) can significantly reduce current consumption. 3:0 0100 R Reserved
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0xDF15: FOCCFG - Frequency Offset Compensation configuration
Bit 7:6 5 Field Name Reserved FOC_BS_CS_GATE 1 Reset R/W R0 R/W If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the CARRIER_SENSE signal goes high. The frequency compensation loop gain to be used before a sync word is detected. Setting 0 (00) 1 (01) 2 (10) 3 (11) 2 FOC_POST_K 1 R/W Freq. compensation loop gain before sync word K 2K 3K 4K Description
4:3
FOC_PRE_K[1:0]
2 (10)
R/W
The frequency compensation loop gain to be used after a sync word is detected. Setting 0 1 Freq. compensation loop gain after sync word Same as FOC_PRE_K K/2
1:0
FOC_LIMIT[1:0]
2 (10)
R/W
The saturation point for the frequency offset compensation algorithm: Setting 0 (00) 1 (01) 2 (10) 3 (11) Saturation point (max compensated offset) 0 (no frequency offset compensation) BWCHAN/8 BWCHAN/4 BWCHAN/2
Frequency offset compensation is not supported for OOK; Always use FOC_LIMIT=0 with this modulation format.
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0xDF16: BSCFG - Bit Synchronization configuration
Bit 7:6 Field Name BS_PRE_KI[1:0] Reset 1 (01) R/W R/W Description The clock recovery feedback loop integral gain to be used before a sync word is detected (used to correct offsets in data rate): Setting 0 (00) 1 (01) 2 (10) 3 (11) 5:4 BS_PRE_KP[1:0] 2 (10) R/W Clock recovery loop integral gain before sync word KI 2KI 3KI 4KI
The clock recovery feedback loop proportional gain to be used before a sync word is detected. Setting 0 (00) 1 (01) 2 (10) 3 (11) Clock recovery loop proportional gain before sync word KP 2KP 3KP 4KP
3
BS_POST_KI
1
R/W
The clock recovery feedback loop integral gain to be used after a sync word is detected. Setting 0 1 Clock recovery loop integral gain after sync word Same as BS_PRE_KI KI /2
2
BS_POST_KP
1
R/W
The clock recovery feedback loop proportional gain to be used after a sync word is detected. Setting 0 1 Clock recovery loop proportional gain after sync word Same as BS_PRE_KP KP
1:0
BS_LIMIT[1:0]
0 (00)
R/W
The saturation point for the data rate offset compensation algorithm: Setting 0 (00) 1 (01) 2 (10) 3 (11) Data rate offset saturation (max data rate difference) 0 (No data rate offset compensation performed) 3.125% data rate offset 6.25% data rate offset 12.5% data rate offset
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0xDF17: AGCCTRL2 - AGC control
Bit 7: 6 Field Name MAX_DVGA_GAIN[1:0] Reset 0 (00) R/W R/W Description Reduces the maximum allowable DVGA gain. Setting 0 (00) 1 (01) 2 (10) 3 (11) 5: 3 MAX_LNA_GAIN[2:0] 0 (000) R/W Allowable DVGA settings All gain settings can be used The highest gain setting can not be used The 2 highest gain settings can not be used The 3 highest gain settings can not be used
Sets the maximum allowable LNA + LNA 2 gain relative to the maximum possible gain. Setting 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Maximum allowable LNA + LNA 2 gain Maximum possible LNA + LNA 2 gain Approx. 2.6 dB below maximum possible gain Approx. 6.1 dB below maximum possible gain Approx. 7.4 dB below maximum possible gain Approx. 9.2 dB below maximum possible gain Approx. 11.5 dB below maximum possible gain Approx. 14.6 dB below maximum possible gain Approx. 17.1 dB below maximum possible gain
2: 0
MAGN_TARGET[2:0]
3 (011)
R/W
These bits set the target value for the averaged amplitude from the digital channel filter (1 LSB = 0 dB). Setting 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Target amplitude from channel filter 24 dB 27 dB 30 dB 33 dB 36 dB 38 dB 40 dB 42 dB
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0xDF18: AGCCTRL1 - AGC control
Bit 7 6 Field Name Reserved AGC_LNA_PRIORITY 1 Reset R/W R0 R/W Selects between two different strategies for LNA and LNA 2 gain adjustment. When 1, the LNA gain is decreased first. When 0, the LNA 2 gain is decreased to minimum before decreasing LNA gain. Sets the relative change threshold for asserting carrier sense Setting 0 (00) 1 (01) 2 (10) 3 (11) 3:0 CARRIER_SENSE_ABS_THR[3:0] 0 (0000) R/W Carrier sense relative threshold Relative carrier sense threshold disabled 6 dB increase in RSSI value 10 dB increase in RSSI value 14 dB increase in RSSI value Description
5:4
CARRIER_SENSE_REL_THR[1:0]
0 (00)
R/W
Sets the absolute RSSI threshold for asserting carrier sense. The 2-complement signed threshold is programmed in steps of 1 dB and is relative to the MAGN_TARGET setting. Setting Carrier sense absolute threshold (Equal to channel filter amplitude when AGC has not decreased gain) -8 (1000) -7 (1001) ... -1 (1111) 0 (0000) 1 (0001) ... 7 (0111) Absolute carrier sense threshold disabled 7 dB below MAGN_TARGET setting ... 1 dB below MAGN_TARGET setting At MAGN_TARGET setting 1 dB above MAGN_TARGET setting ... 7 dB above MAGN_TARGET setting
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0xDF19: AGCCTRL0 - AGC control
Bit 7:6 Field Name HYST_LEVEL[1:0] Reset 2 (10) R/W R/W Description Sets the level of hysteresis on the magnitude deviation (internal AGC signal that determine gain changes). Setting 0 (00) 1 (01) 2 (10) 3 (11) 5:4 WAIT_TIME[1:0] 1 (01) R/W Description No hysteresis, small symmetric dead zone, high gain Low hysteresis, small asymmetric dead zone, medium gain Medium hysteresis, medium asymmetric dead zone, medium gain Large hysteresis, large asymmetric dead zone, low gain
Sets the number of channel filter samples from a gain adjustment has been made until the AGC algorithm starts accumulating new samples. Setting 0 (00) 1 (01) 2 (10) 3 (11) Channel filter samples 8 16 24 32
3:2
AGC_FREEZE[1:0]
0 (00)
R/W
Controls when the AGC gain should be frozen. Setting 0 (00) 1 (01) 2 (10) Function Normal operation. Always adjust gain when required. The gain setting is frozen when a sync word has been found. Manually freeze the analog gain setting and continue to adjust the digital gain. Manually freezes both the analog and the digital gain settings. Used for manually overriding the gain.
3 (11) 1:0 FILTER_LENGTH[1:0] 1 (01) R/W
Sets the averaging length for the amplitude from the channel filter. Setting 0 (00) 1 (01) 2 (10) 3 (11) Channel filter samples 8 16 32 64
0xDF1A: FREND1 - Front end RX configuration
Bit 7:6 5:4 3:2 1:0 Field Name LNA_CURRENT[1:0] LNA2MIX_CURRENT[1:0] LODIV_BUF_CURRENT_RX[1:0] MIX_CURRENT[1:0] Reset 1 (01) 1 (01) 1 (01) 2 (10) R/W R/W R/W R/W R/W Description Adjusts front-end LNA PTAT current output Adjusts front-end PTAT outputs Adjusts current in RX LO buffer (LO input to mixer) Adjusts current in mixer
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0xDF1B: FREND0 - Front end TX configuration
Bit 7:6 5:4 Field Name LODIV_BUF_CURRENT_TX[1:0] Reset 00 01 R/W R0 R/W Description Reserved Adjusts current TX LO buffer (input to PA). The value to use in this field is given by the SmartRF(R) Studio software. Reserved Selects PA power setting. This value is an index to the PATABLE, which can be programmed with up to 8 different PA settings. The PATABLE settings from index `0' to the PA_POWER value are used for power rampup/ramp-down at the start/end of transmission in all TX modulation formats.
3 2:0
PA_POWER[2:0]
0 000
R0 R/W
0xDF1C: FSCAL3 - Frequency synthesizer calibration
Bit 7:6 Field Name FSCAL3[7:6] Reset 2 (10) R/W R/W Description Frequency synthesizer calibration configuration. The value to write in this register before calibration is given by the SmartRF(R) Studio software. Disable charge pump calibration stage when 0 Frequency synthesizer calibration result register. Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency.
5:4 3:0
CHP_CURR_CAL_EN[1:0] FSCAL3[3:0]
2 (10) 9 (1001)
R/W R/W
0xDF1D: FSCAL2 - Frequency synthesizer calibration
Bit 7:6 5:0 Field Name FSCAL2[5:0] Reset 00 0x0A R/W R0 R/W Description Reserved Frequency synthesizer calibration result register. Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency.
0xDF1E: FSCAL1 - Frequency synthesizer calibration
Bit 7:6 5:0 Field Name FSCAL1[5:0] Reset 00 0x02 R/W R0 R/W Description Reserved Frequency synthesizer calibration result register. Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency.
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0xDF1F: FSCAL0 - Frequency synthesizer calibration
Bit 7 4:0 Field Name FSCAL0[6:0] Reset 0 0x0D R/W R0 R/W Description Reserved Frequency synthesizer calibration control. The value to use in this register is given by the SmartRF(R) Studio software.
0xDF27: PA_TABLE7 - PA power setting 7
Bit 7:0 Field Name PA_TABLE7[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 7 Currently used PA output power is selected by FREND0.PA_POWER[2:0]
0xDF28: PA_TABLE6 - PA power setting 6
Bit 7:0 Field Name PA_TABLE6[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 6 Currently used PA output power is selected by FREND0.PA_POWER[2:0]
0xDF29: PA_TABLE5 - PA power setting 5
Bit 7:0 Field Name PA_TABLE5[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 5 Currently used PA output power is selected by FREND0.PA_POWER[2:0]
0xDF2A: PA_TABLE4 - PA power setting 4
Bit 7:0 Field Name PA_TABLE4[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 4 Currently used PA output power is selected by FREND0.PA_POWER[2:0]
0xDF2B: PA_TABLE3 - PA power setting 3
Bit 7:0 Field Name PA_TABLE3[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 3 Currently used PA output power is selected by FREND0.PA_POWER[2:0]
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0xDF2C: PA_TABLE2 - PA power setting 2
Bit 7:0 Field Name PA_TABLE2[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 2 Currently used PA output power is selected by FREND0.PA_POWER[2:0]
0xDF2D: PA_TABLE1- PA power setting 1
Bit 7:0 Field Name PA_TABLE1[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 1 Currently used PA output power is selected by FREND0.PA_POWER[2:0]
0xDF2E: PA_TABLE0 - PA power setting 0
Bit 7:0 Field Name PA_TABLE0[7:0] Reset 0xC6 R/W R/W Description Power amplifier output power setting 0 Currently used PA output power is selected by FREND0.PA_POWER[2:0]
0xDF36: PARTNUM - Chip Identifier
Bit 7:0 Field Name PARTNUM[7:0] Reset 0x81 CC2510FX 0x91 CC2511Fx R/W R Description Chip part number
0xDF37: VERSION - Chip Version
Bit 7:0 Field Name VERSION[7:0] Reset 0x03 R/W R Description Chip version number.
0xDF38: FREQEST - Frequency Offset Estimate from demodulator
Bit 7:0 Field Name FREQOFF_EST Reset R/W R Description The estimated frequency offset (two's complement) of the 14 carrier. Resolution is FXTAL/2 (1.5kHz-1.7kHz); range is 186kHz to 217kHz, dependent of XTAL frequency. Frequency offset compensation is only supported for FSK and MSK modulation. This register will read 0 when using OOK modulation.
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0xDF39: LQI - Demodulator estimate for Link Quality
Bit 7 6:0 Field Name CRC OK LQI_EST[6:0] Reset R/W R R Description The last CRC comparison matched. Cleared when entering/restarting RX mode. The Link Quality Indicator estimates how easily a received signal can be demodulated. Calculated over the 64 symbols following the sync word (first 8 packet bytes for 2-ary modulation, first 16 packet bytes for 4-ary modulation).
0xDF3A: RSSI - Received signal strength indication
Bit 7:0 Field Name RSSI Reset R/W R Description Received signal strength indicator
0xDF3B: MARCSTATE - Main Radio Control State Machine state
Bit 7:5 4:0 Field Name Reserved MARC_STATE[4:0] Reset R/W R0 R Main Radio Control FSM State Value 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 14 (0x0E) 15 (0x0F) 16 (0x10) 17 (0x11) 18 (0x12) 19 (0x13) 20 (0x14) 21 (0x15) 22 (0x16) State name SLEEP IDLE XOFF VCOON_MC REGON_MC MANCAL VCOON REGON STARTCAL BWBOOST FS_LOCK IFADCON ENDCAL RX RX_END RX_RST TXRX_SWITCH RX_OVERFLOW FSTXON TX TX_END RXTX_SWITCH TX_UNDERFLOW State (Figure 50, page 209) SLEEP IDLE XOFF MANCAL MANCAL MANCAL FS_WAKEUP FS_WAKEUP CALIBRATE SETTLING SETTLING SETTLING CALIBRATE RX RX RX TXRX_SETTLING RX_OVERFLOW FSTXON TX TX RXTX_SETTLING TX_UNDERFLOW Description
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0xDF3C: PKTSTATUS - Current GDOx status and packet status
Bit 7 6 5 4 3 2:0 Field Name CRC_OK CS PQT_REACHED CCA SFD Reset 0 0 0 0 0 000 R/W R R R R R R0 Description The last CRC comparison matched. Cleared when entering/restarting RX mode. Carrier sense Preamble Quality reached Clear channel assessment Start of Frame Delimiter found Not used.
0xDF3D: VCO_VC_DAC - Current setting from PLL calibration module
Bit 7:0 Field Name VCO_VC_DAC[7:0] Reset R/W R Description Status register for test only.
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16 Voltage Regulators
The CC2510FX/CC2511Fx includes a low drop-out voltage regulator. This is used to provide a 1.8 V power supply to the CC2510FX/CC2511Fx digital power supply. The voltage regulator should not be used to provide power to external circuits because of limited power sourcing capability and also due to noise considerations. The voltage regulator input pin AVDD_DREG is to be connected to the unregulated 2.0 V to 3.6 V power supply. The output of the digital regulator is connected internally in the CC2510FX/CC2511Fx to the digital power supply. The voltage regulator requires an external decoupling capacitor connected to the DCOUPL pin as described in section 11 on page 31. 16.1 Voltage Regulator Power-on The voltage regulator is disabled when the CC2510FX/CC2511Fx is placed in power modes PM2 or PM3 (see section 13.10). When the voltage regulator is disabled, register and RAM contents will be retained while the unregulated 2.0 V - 3.6 V power supply is present.
17 Radio Test Output signals
For debug and test purposes, a number of internal status signals in the radio may be output on the port pins P1_7 - P1_5. This debug option is controlled through the RF registers IOCFG2-IOCFG0 . Table 69 shows the value written to IOCFGx.GDOx_CFG[5:0] with the corresponding internal signals that will be output in each case.
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GDO0_CFG[5:0] GDO1_CFG[5:0] GDO2_CFG[5:0]
0-7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30-46 47 48-63 Description Not in use Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value. Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting) Lock detector output Serial Clock. Synchronous to the data in synchronous serial mode. Data is set up on the falling edge and is read on the rising edge of SERIAL_CLK. Serial Synchronous Data Output. Used for synchronous serial mode. The MCU must read DO on the rising edge of SERIAL_CLK. Data is set up on the falling edge by CC1100. Serial transparent Data Output. Used for asynchronous serial mode. Carrier sense. High if RSSI level is above threshold. CRC OK. The last CRC comparison matched. Cleared when entering/restarting RX mode. ADC I/Q - serialized Decimation filter output I/Q + channel filter I/Q + CORDIC + GAIN Demodulator backend key signals (PSK) Demodulator backend key signals (FSK) Data filter output Not in use RX_HARD_DATA[1] RX_HARD_DATA[0] FPLL CLK_PRE VCO_CURR_COMP PA_PD LNA_PD RX_SYMBOL_TICK Not in use HW to 0 (HW1 achieved with _INV signal) Not in use
Table 69: Debug output signals
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18 Evaluation Software
provides users of CC2510FX/CC2511Fx with a software program, SmartRF(R) Studio, which may be used for radio performance and functionality evaluation. SmartRF(R) Studio runs on Microsoft Windows 95/98 and Microsoft Windows NT/XP/2000. Chipcon SmartRF(R) Studio can be downloaded from Chipcon's web page: http://www.ti.com/lpw http://www.chipcon.com
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19 Register overview
DPH0 (0x83) - Data Pointer 0 High Byte............................................................................... 38 DPL0 (0x82) - Data Pointer 0 Low Byte ................................................................................ 38 DPH1 (0x85) - Data Pointer 1 High Byte............................................................................... 38 DPL1 (0x84) - Data Pointer 1 Low Byte ................................................................................ 38 DPS (0x92) - Data Pointer Select ........................................................................................... 38 MPAGE (0x93)- Memory Page Select ................................................................................... 39 PSW (0xD0) - Program Status Word...................................................................................... 43 ACC (0xE0) - Accumulator.................................................................................................... 43 B (0xF0) - B Register ............................................................................................................. 44 SP (0x81) - Stack Pointer ....................................................................................................... 44 IEN0 (0xA8) - Interrupt Enable 0 Register............................................................................. 51 IEN1 (0xB8) - Interrupt Enable 1 Register............................................................................. 52 IEN2 (0x9A) - Interrupt Enable 2 Register............................................................................. 53 TCON (0x88) - Interrupt Flag ................................................................................................ 55 S0CON (0x98) - Interrupt Flag 2............................................................................................ 56 S1CON (0x9B) - Interrupt Flag 3 ........................................................................................... 56 IRCON (0xC0) - Interrupt Flag 4 ........................................................................................... 57 IRCON2 (0xE8) - Interrupt Flag 5 ......................................................................................... 58 IP1 (0xB9) - Interrupt Priority 1 ............................................................................................. 59 IP0 (0xA9) - Interrupt Priority 0............................................................................................. 59 MEMCTR (0xC7) - Memory Arbiter Control ........................................................................ 65 P0 (0x80) - Port 0 ................................................................................................................... 71 P1 (0x90) - Port 1 ................................................................................................................... 71 P2 (0xA0) - Port 2................................................................................................................... 71 PERCFG (0xF1) - Peripheral Control .................................................................................... 71 ADCCFG (0xF2) - ADC Input Configuration........................................................................ 72 P0SEL (0xF3) - Port 0 Function Select .................................................................................. 72 P1SEL (0xF4) - Port 1 Function Select .................................................................................. 73 P2SEL (0xF5) - Port 2 Function Select .................................................................................. 74 P0DIR (0xFD) - Port 0 Direction ........................................................................................... 75 P1DIR (0xFE) - Port 1 Direction............................................................................................ 76 P2DIR (0xFF) - Port 2 Direction ............................................................................................ 77 P0INP (0x8F) - Port 0 Input Mode ......................................................................................... 78 P1INP (0xF6) - Port 1 Input Mode ......................................................................................... 79 P2INP (0xF7) - Port 2 Input Mode ......................................................................................... 80 P0IFG (0x89) - Port 0 Interrupt Status Flag ........................................................................... 81 P1IFG (0x8A) - Port 1 Interrupt Status Flag .......................................................................... 81 P2IFG (0x8B) - Port 2 Interrupt Status Flag........................................................................... 81 PICTL (0x8C) - Port Interrupt Control................................................................................... 82 P1IEN (0x8D) - Port 1 Interrupt Mask ................................................................................... 83 DMAARM (0xD6) - DMA Channel Arm .............................................................................. 93 DMAREQ (0xD7) - DMA Channel Start Request and Status................................................ 94 DMA0CFGH (0xD5) - DMA Channel 0 Configuration Address High Byte ......................... 94 DMA0CFGL (0xD4) - DMA Channel 0 Configuration Address Low Byte .......................... 94 DMA1CFGH (0xD3) - DMA Channel 1-4 Configuration Address High Byte...................... 95 DMA1CFGL (0xD2) - DMA Channel 1-4 Configuration Address Low Byte....................... 95 DMAIRQ (0xD1) - DMA Interrupt Flag ................................................................................ 95 ENDIAN (0x95) - USB Endianess Control (CC2511Fx) ......................................................... 96 T1CNTH (0xE3) - Timer 1 Counter High ............................................................................ 106 T1CNTL (0xE2) - Timer 1 Counter Low ............................................................................. 106
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T1CTL (0xE4) - Timer 1 Control and Status........................................................................ 106 T1CCTL0 (0xE5) - Timer 1 Channel 0 Capture/Compare Control...................................... 107 T1CC0H (0xDB) - Timer 1 Channel 0 Capture/Compare Value High ................................ 107 T1CC0L (0xDA) - Timer 1 Channel 0 Capture/Compare Value Low ................................. 107 T1CCTL1 (0xE6) - Timer 1 Channel 1 Capture/Compare Control...................................... 108 T1CC1H (0xDD) - Timer 1 Channel 1 Capture/Compare Value High ................................ 108 T1CC1L (0xDC) - Timer 1 Channel 1 Capture/Compare Value Low ................................. 109 T1CCTL2 (0xE7) - Timer 1 Channel 2 Capture/Compare Control...................................... 109 T1CC2H (0xDF) - Timer 1 Channel 2 Capture/Compare Value High................................. 109 T1CC2L (0xDE) - Timer 1 Channel 2 Capture/Compare Value Low.................................. 110 T2CTL (0x9E) - Timer 2 Control ......................................................................................... 112 T2CT (0x9C) - Timer 2 Count.............................................................................................. 112 T2PR (0x9D) - Timer 2 Prescaler......................................................................................... 112 WORTIME0 (0xA5) - Sleep Timer Low Byte ..................................................................... 114 WORTIME1 (0xA6) - Sleep Timer High Byte .................................................................... 114 WOREVT1 (0xA4) - Sleep Timer Event0 Timeout High .................................................... 114 WOREVT0 (0xA3) - Sleep Timer Event0 Timeout Low..................................................... 114 WORCTL (0xA2) - Sleep Timer Control............................................................................. 115 WORIRQ (0xA1) - Sleep Timer Interrupt Control............................................................... 115 T3CNT (0xCA) - Timer 3 Counter....................................................................................... 120 T3CTL (0xCB) - Timer 3 Control ........................................................................................ 120 T3CCTL0 (0xCC) - Timer 3 Channel 0 Capture/Compare Control..................................... 121 T3CC0 (0xCD) - Timer 3 Channel 0 Capture/Compare Value ............................................ 121 T3CCTL1 (0xCE) - Timer 3 Channel 1 Capture/Compare Control ..................................... 122 T3CC1 (0xCF) - Timer 3 Channel 1 Capture/Compare Value............................................. 122 T4CNT (0xEA) - Timer 4 Counter ....................................................................................... 122 T4CTL (0xEB) - Timer 4 Control ........................................................................................ 123 T4CCTL0 (0xEC) - Timer 4 Channel 0 Capture/Compare Control ..................................... 124 T4CC0 (0xED) - Timer 4 Channel 0 Capture/Compare Value ............................................ 124 T4CCTL1 (0xEE) - Timer 4 Channel 1 Capture/Compare Control ..................................... 125 T4CC1 (0xEF) - Timer 4 Channel 1 Capture/Compare Value ............................................. 125 TIMIF (0xD8) - Timers 1/3/4 Interrupt Mask/Flag .............................................................. 126 ADCL (0xBA) - ADC Data Low.......................................................................................... 130 ADCH (0xBB) - ADC Data High......................................................................................... 130 ADCCON1 (0xB4) - ADC Control 1 ................................................................................... 130 ADCCON2 (0xB5) - ADC Control 2 ................................................................................... 131 ADCCON3 (0xB6) - ADC Control 3 ................................................................................... 132 RNDL (0xBC) - Random Number Generator Data Low Byte ............................................. 134 RNDH (0xBD) - Random Number Generator Data High Byte ............................................ 134 ENCCS (0xB3) - Encryption Control and Status ................................................................. 139 ENCDI (0xB1) - Encryption Input Data.............................................................................. 139 ENCDO (0xB2) - Encryption Output Data.......................................................................... 139 PCON (0x87) - Power Mode Control ................................................................................... 142 SLEEP (0xBE) - Sleep Mode Control ................................................................................. 142 CLKCON (0xC6) - Clock Control....................................................................................... 143 WDCTL (0xC9) - Watchdog Timer Control ....................................................................... 146 U0CSR (0x86) - USART 0 Control and Status .................................................................... 152 U0UCR (0xC4) - USART 0 UART Control ........................................................................ 153 U0GCR (0xC5) - USART 0 Generic Control....................................................................... 154 U0DBUF (0xC1) - USART 0 Receive/Transmit Data Buffer.............................................. 154 U0BAUD (0xC2) - USART 0 Baud Rate Control................................................................ 154 U1CSR (0xF8) - USART 1 Control and Status .................................................................... 155 U1UCR (0xFB) - USART 1 UART Control ........................................................................ 156
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A 252 Page 245 of
CC2510FX / CC2511Fx
U1GCR (0xFC) - USART 1 Generic Control....................................................................... 157 U1DBUF (0xF9) - USART 1 Receive/Transmit Data Buffer .............................................. 157 U1BAUD (0xFA) - USART 1 Baud Rate Control ............................................................... 157 FCTL (0xAE) - Flash Control .............................................................................................. 189 FWDATA (0xAF) - Flash Write Data .................................................................................. 189 FADDRH (0xAD) - Flash Address High Byte ..................................................................... 189 FADDRL (0xAC) - Flash Address Low Byte ...................................................................... 189 FWT (0xAB) - Flash Write Timing ...................................................................................... 189 RFIF (0xE9) - RF Interrupt Flags ......................................................................................... 194 RFIM (0x91) - RF Interrupt Mask........................................................................................ 195
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A 252
Page 246 of
CC2510FX / CC2511Fx
20 Package Description (QLP 36)
All dimensions are in millimeters, angles in degrees. NOTE: The CC2510FX/CC2511Fx is available in RoHS lead-free package only. Compliant with JEDEC: MO-220.
Figure 58: Package dimensions drawing
Quad Leadless Package (QLP) A QLP36 Min 0.80 0.85 Max 0.90 A1 0.005 0.025 0.045 A2 0.60 0.65 0.70 D 5.90 6.00 6.10 D1 5.65 5.75 5.85 E 5.90 6.00 6.10 E1 5.65 5.75 5.85 0.50 e b 0.18 0.23 0.30 L 0.45 0.55 0.65 4.40 4.40 D2 1.75 E2 1.75
The overall package height is 0.85 +/- 0.05 All dimensions in mm
Table 70: Package dimensions
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 247 of 252
CC2510FX / CC2511Fx
20.1 Recommended PCB layout for package (QLP 36)
Figure 59: Recommended PCB layout for QLP 36 package Note: The figure is an illustration only and not to scale. There are nine 14 mil diameter via holes distributed symmetrically in the ground pad under the package. See also the CC2510FX EM reference design. 20.2 Package thermal properties
Thermal resistance Air velocity [m/s] Rth,j-a [K/W] 0 32
Table 71: Thermal properties of QLP 36 package 20.3 Soldering information The recommendations for lead-free reflow in IPC/JEDEC J-STD-020C should be followed. 20.4 Tray specification
Tray Specification Package QLP 36 Tray Length 322.6 mm Tray Width 135.9 mm Tray Height 7.62 mm Units per Tray 490
Table 72: Tray specification
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 248 of 252
CC2510FX / CC2511Fx
20.5 Carrier tape and reel specification Carrier tape and reel is in accordance with EIA Specification 481.
Tape and Reel Specification Package QLP 36 Carrier Tape Width 16 mm Component Pitch 12 mm Hole Pitch 4 mm Reel Diameter 13 inches Reel Hub Diameter 7 inches Units per Reel 2500
Table 73: Carrier tape and reel specification
21 Ordering Information
Ordering part number CC2510F8RSP Description Minimum Order Quantity 490
8 kB FLASH, 1 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray.
CC2510F8RSPR
8 kB FLASH, 1 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel.
2500
CC2510F16RSP
16 kB FLASH, 2 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray.
490
CC2510F16RSPR
16 kB FLASH, 2 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel.
2500
CC2510F32RSP
32 kB FLASH, 4 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray.
490
CC2510F32RSPR
32 kB FLASH, 4 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel.
2500
CC2511F8RSP
8 kB FLASH, 1 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray.
490
CC2511F8RSPR
8 kB FLASH, 1 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel.
2500
CC2511F16RSP
16 kB FLASH, 2 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray.
490
CC2511F16RSPR
16 kB FLASH, 2 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel.
2500
CC2511F32RSP
32 kB FLASH, 4 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray.
490
CC2511F32RSPR
32 kB FLASH, 4 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel.
2500
CC2510-CC2511DK
CC2510FX and CC2511Fx Development Kit
1
Table 74: Ordering Information
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 249 of 252
CC2510FX / CC2511Fx
22 General Information
22.1 Document History
Revision 1.0 1.01 1.1 1.2 Date 2005-11-17 2006-05-11 2006-05-30 2006-07-06 Description/Changes First release, preliminary Preliminary status updated CC2511Fx, CC2510F8 and CC2510F16 added to datasheet. Changed recommended PCB layout for package (QLP 36), fig 59
Table 75: Document history 22.2 Product Status Definitions
Data Sheet Identification Advance Information Product Status Planned or Under Development Engineering Samples and Pre-Production Prototypes Definition This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. The product at this point is not yet fully qualified. This data sheet contains the final specifications. Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains specifications on a product that has been discontinued by Chipcon. The data sheet is printed for reference information only.
Preliminary
No Identification Noted
Full Production
Obsolete
Not In Production
Table 76: Product Status Definitions
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 250 of 252
CC2510FX / CC2511Fx
23 Address Information
Texas Instruments Norway AS Gaustadalleen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 Web site: http://www.ti.com/lpw
24 TI Worldwide Technical Support Internet
TI Semiconductor Product Information Center Home Page: TI Semiconductor KnowledgeBase Home Page: support.ti.com support.ti.com/sc/knowledgebase
Product Information Centers
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CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 251 of 252
CC2510FX / CC2511Fx
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Fax Email Internet
CC2510FX/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A
Page 252 of 252
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